The cell roadmap is for 45nm chips by 2010 and be about 5 times more powerful with teraflop performance
The roadmap shows the already scheduled die shrink to 65 nm (just introduced March 12, 2007, making the Cell considerably cheaper to produce and reducing power consumption. Its die with 9 processors (1 PPE + 8 SPEs) is currently still 235 mm² in size and therefore at the level of IBM's top server chip POWER5+ with 243 mm² (for comparison: Intel Core2Duo - 143 mm²).
IBMs Dual-Cell Bladeserver hardware uses up to 315 Watts and we learn that Sony puts a 380 Watts PSU into their Playstation 3, a very comfortable power margin for the quiet-running performance product.
A new line of mid-class Cells is set to debut in 2008 with only 4 SPEs and a particular focus on low power consumption with cheap producibility in bulk silicon vs. the more complex SOI technology. Toshiba plans to scale it down to a single-SPU version for ultra-portable devices in 2010.
At the other end of the performance scale the renewed 5-years alliance will culminate in a teraflops processor. According to Cell architect Jim Kahle the performance goal can be achieved by 2010 with a new 32 SPE Cell die.