Terabyte bandwidth initiative

In a world with 100 cores on a single chip, how do you get enough data onto the chip to keep all those cores fed?

Rambus is working on technology that does 32 data transfers per clock beat, so that each line can transmit 32 bits per clock cycle. That’s a ton of per-pin bandwidth, and it means that bandwidth will scale pretty dramatically even at low clockspeeds as you add bus wires. For instance, on a 500MHz clock that’s 16Gbps per wire, a number that can be doubled by simply adding a second data link.

16 DRAMs x 16 Gbps x 32 bits per DRAM gives you 1 TB/s of bandwidth onto an SoC, hence the name of the initiative.

Intel is also looking to differential signaling for the medium-term future of board-level, chip-to-chip bandwidth in the 15Gbps range. The consensus seems to be that single-ended signaling isn’t suitable for higher transfer rates, due to noise problems.

TBI is still in the “research initiative” phase, much like Intel’s Terascale initiative. And like Intel’s Terascale, Rambus has built a prototype to test some of the ideas mentioned above. The TBI prototype consists of three 65nm, chips, an SoC stand-in, and two simulated DRAMs. For the latter, Rambus tried to mimic the characteristics of a DRAM that might exist in the 2010-2011 timeframe, and they were able to get a potentially usable signal (it would need cleanup) between the SoC and the DRAMs at a 32x data rate.

Rambus is aiming for 2010 or later with the technologies in TBI.

UPDATE: as noted in the comments, there is no guarantee that Rambus or Intel will be successful or to what degree.

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