The 3D IC, which was processed on 8-inch wafers with industry standard 0.18-micron CMOS technologies both at NNFC and SNF, contains 128 million vertically oriented devices as a test vehicle, and was uniquely processed at low temperatures — below 400 degree Celsius, the parties explained. Also, a sub-micron-thick single crystalline silicon layer was initially formed above the silicon substrate with two metal interconnect layers, followed by vertical devices and additional metal layer.
EE Times also has coverage and a video clip discussing the 3D IC
“The cost of BeSang’s 3-D chips should be much lower, because you are reducing the overall chip area by putting all your logic in one process on the bottom wafer, putting all of your memory, using a different process, on the top wafer, and using the conventional vias to interconnect them,” Sze predicted.
This technology (shown left) forms full 3D interconnects below and above the vertical devices, whereas conventional semiconductor technologies contain planar devices on the surface of the semiconductor substrate and interconnects only above the planar devices.
Stanford University Professor and head of SNF, Dr. Dr. Yoshio Nishi explained in a statement, “One of unique features of BeSang’s 3D IC is the capability of unrestricted 3D interconnections using conventional via technologies that does not require wafer alignment nor through-silicon vias for 3D interconnects. Conventional CMOS technology is facing its scaling limits. Therefore, this emerging 3D IC technology will extend the lifespan of CMOS technology, because it is an excellent alternative way to accommodate more devices on a given wafer area.”
While chip level 3D IC has been explored for many years by the semiconductor industry, market introduction of chip level 3D IC has been delayed due to technical challenges, including high-temperature processing, defects in semiconductor layers, limited 3D interconnections, and a complex process.
However, BeSang said it will be able to address these problems and has generated high-performance and reliable devices on single crystalline silicon layers that are subsequently formed above another silicon substrate at low temperature, which is an important aspect of this technology.
FURTHER READING
The BeSang website
The Stanford Nanofabrication facility site
Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
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