Dharmendra S Modha’s, IBM Almaden, talk on his brain emulation project was one of the highlights of the 2008 Singularity Summit. The Brain Emulation Roadmap was not presented at the Singularity Summit but was recently published online and relates to the brain emulation work.
The rat-scale model (55 million neurons, 442 billion synapses) is about 3.5 times bigger than our previous work on mouse-scale model (16 million neurons, 128 billion synapses) and eight times bigger than (almost) half-mouse-scale models (8 million neurons, 50 million synapses).
The essence of an efficient cortical simulator, C2, is as follows:
1. For every neuron:
a. For every clock step (say 1 ms):
i. Update the state of each neuron
ii. If the neuron fires, generate an event for each synapse that
the neuron is post-synaptic to and pre-synaptic to.
2. For every synapse:
When it receives a pre- or post-synaptic event,
update its state and, if necessary, the state of the post-synaptic neuron.
Our focus is on simulating only those details that lead us towards insights into brain’s high-level computational principles. Elucidation of such high-level principles will lead, we hope, to novel cognitive systems, computing architectures, programming paradigms, and numerous practical applications.
The human cortex has about 22 billion neurons which is roughly a factor of 400 larger than our rat-scale model which has 55 million neurons. We used a BlueGene/L with 92 TF and 8 TB to carry out rat-scale simulations in near real-time [one tenth speed]. So, by naïve extrapolation, one would require at least a machine with a computation capacity of 36.8 PF and a memory capacity of 3.2 PB. Furthermore, assuming that there are 8,000 synapses per neuron, that neurons fire at an average rate of 1 Hz, and that each spike message can be communicated in, say, 66 Bytes. One would need an aggregate communication bandwidth of ~ 2 PBps.
Scaling the synapses from rat brain to human brain is main driver in the computer power needed for brain emulation. There are petaflop supercomputers now so if such a system were dedicated to brain emulation a system ten times larger than the rat brain could be simulated.
An informal poll among workshop attendees produced a range of estimates where the required resolution for Whole Brain Emulation (WBE) is. The consensus appeared to be level 4‐6. Two participants were more optimistic about high level models, while two suggested that elements on level 8‐9 may be necessary at least initially (but that the bulk of mature emulation, once the basics were understood, could occur on level 4‐5). To achieve emulation on this level, the consensus was that 5×5×50 nm scanning resolution would be needed. This roadmap will hence focus on level 4‐6 models, while being open for that deeper levels may turn out to be needed.
Special hardware for WBE
It is possible that WBE can be achieved more efficiently using dedicated hardware rather than generic hardware Dedicated neural network chips have reached up to 1.7 billion synaptic updates (and 337 million synaptic adjustments) per second for ANN models (Kondo, Koshiba et al., 1996), which is approaching current supercomputing speeds for more complex models. Recently, there has been some development of FPGAs for running complex neuron simulations, producing an order of magnitude faster simulation for a motorneuron than a software implementation (four times real‐time, 8M compartments/s) (Weinstein and Lee, 2005). A FPGA implementation has the advantage of being programmable, not requiring WBE‐special purpose hardware. Other advantages include that as long as there is chip space, more complex models do not require more processing time and that precision can be adjusted to suit the model and reduce space requirements. However, scaling up to large and densely interconnected networks will require developing new techniques (Weinstein and Lee, 2006). A better understanding of the neocortical architecture may serve to produce hardware architectures that fit it well (Daisy project, 2008). It has been suggested that using FPGAs could increase computational speeds in network simulations by up to two orders of magnitude, and in turn enable testing grounds for developing special purpose WBE chips (Markram, 2006).
It may also be possible to use embedded processor technology to manufacture large amounts of dedicated hardware relatively cheaply. A study of high resolution climate modelling in the petaflop range found a 24‐ to 34‐fold reduction of cost and about two orders of magnitude smaller power requirements using a custom variant of embedded processor chips (Wehner,Oliker et al., 2008).
Whole Brain Emulation (WBE) on the neuronal/synaptic level requires relatively modest increases in microscopy resolution, a less trivial development of automation for scanning and image processing, a research push at the problem of inferring functional properties of neurons and synapses, and relatively business‐as‐usual development of computational neuroscience models and computer hardware. This assumes that this is the appropriate level of description of the brain, and that we find ways of accurately simulating the subsystems that occurs on this level. Conversely, pursuing this research agenda will also help detect whether there are low‐level effects that have significant influence on higher level systems, requiring an increase in simulation and scanning resolution.