Sematech : Leading Ways to Continue Moore’s Law

During a presentation on June 26, 2009 chip-making consortium Sematech outlined ways to enable Moore’s Law

Sematech also warned about a gap in Extreme Ultra-violet mask inspection tools.

To enable EUV in mass production fabs, IC makers must get their hands on defect-free photomasks. Today’s EUV masks have 1 defect per cm^2 at 18-nm. The ultimate goal is to devise EUV masks with 0.003 defects per cm^2 at 18-nm. In other words, there is a ”25X gap” in terms of enabling defect-free masks for EUV pilot production and a ”100X gap” for EUV fab production

Technology that can help continue Moore’s Law
1. Zero low-k interface. In current 45-nm designs from Intel Corp., there is the silicon substrate and the high-k/metal-gate scheme. A low-k material sits between the silicon and high-k structure. But with a zero low-k interface, the low-k material is removed, enabling more drive current and less leakage. This is an option for the 16-nm node or sooner.

2. Single metal gate stack. Instead of a traditional transistor, a high-k/metal-gate scheme makes use of a single metal gate stack. This improves the performance but lowers the power consumption of the device.

3. Gate stacks on III-V semiconductors. Intel, Sematech and others have talked about using an InGaAs/high-k interface for future designs. Would also boost performance and lower power.

4. Quantum-well MOSFETs. The use of silicon-germanium on silicon as a means to boost performance. Intel recently demonstrated a high-speed, low-power quantum well field effect transistor. The p-channel structure will be based on a 40-nm indium antimonide (InSb) material.

III-V MOSFETs for future CMOS transistor applications

Cross-sectional schematic view of a) a PHEMT and b) a III-V quantum well MOSFET with virtual drain/source extensions.

5. 3-D chips using through-silicon-via (TSVs). Sematech on Friday disclosed plans to set up a 300-mm R&D ”test bed” [by 2010] for the production of 3-D devices based on TSV technology.

Report progress in areas such as next generation high-k/metal gate (HKMG) materials, advanced flash memory, planar and non-planar CMOS technologies and HKMG defect metrology

La-doped Metal/High-K nMOSFET for Sub-32nm HP and LSTP Application – Investigates the suitability of nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm low standby power (LSTP) and high performance applications.

Extending spectroscopic ellipsometry for identification of electrically active defects in Si/SiO2/high-k/metal gate stacks – Explores a new method using spectroscopic ellipsometry to non-invasively identify oxygen vacancy defects in the bottom interfacial SiO2 layer of the scaled high-k/metal gate stacks.

Reliability Assessment of Low Vt Metal High-k Gate Stacks for High Performance Applications – Describes of reliability characterization techniques and models targeting HKMG lifetime predictions.

Additive Mobility Enhancement and Off-State Current Reduction in SiGe Channel pMOSFETs with Optimized Si Cap and High-k Metal Gate Stacks – Demonstrates high mobility pMOSFETs with high quality epitaxial SiGe films selectively grown on Si (100) substrates.

Band Engineered Tunnel Oxides for Improved TANOS-type Flash Program/Erase with Good Retention and 100K Cycle Endurance – Demonstrates, for the first time, that band-engineered tunnel oxides integrated with a high-k/metal gate can improve program, erase, and endurance in charge-trapped flash memory devices.

High Mobility SiGe Shell-Si Core Omega Gate PFETs – Explores the use of Omega gate-type pFETs with a SiGe shell (high mobility channel) on a Si core.

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