Jeff Welser Interview
Here is the Jeff Welser interview by Sander Olson. Dr. Welser is the Director of the Nanoelectronics Research Initiative (NRI). The NRI was established in 2004 in order to develop post-silicon CMOS computing technologies, which will be needed by 2020 if not earlier. The NRI is hoping that a post-CMOS technology will emerge by 2020. If the NRI succeeds then the exponential growth in computing could continue until the mid 2030s.
Question 1: Tell us about the Semiconductor Research Corporation (SRC) and the Nanoelectronics Research Initiative (NRI).
Answer: The semiconductor Research Corporation is a research consortium that began in the early 1980s. It was started specifically to encourage universities to extend Moore’s law as long as possible. It is funded by both industry and government, and the SRC now oversees several subsidiary programs. One of these subsidiary programs is the NRI, which I direct. The SRC is focused on improving charge-based components, such as field effect transistors (FETs). The NRI, however, is focused on computing and switching technologies that could outperform anything that is currently envisioned from charge based devices. We are hoping that one of these post-CMOS technologies could emerge by 2020.
Question 2: A recent report by iSuppli argued that Moore’s law won’t continue past 2014 due to increasingly high costs. Do you agree?
Answer: I believe that prediction is excessively pessimistic. Although spiraling costs are clearly burdening the semiconductor industry, the industry is responding by creating alliances and pooling R&D resources. Moreover, there are other ways beside scaling to increase chip performance, and these options are being actively researched.
Question 3: What is the biggest technical hurdle that the semiconductor industry faces?
Answer: The single biggest challenge the industry faces relates to power density. The power density of modern microprocessors is too high for us to fully utilize all the transistors at full speed. The industry has reduced voltages to one volt, but can’t realistically go too much below that for room temperature operation. This inability to continue to scale the voltage is a primary contributor to the increasing power density and imposes fundamental limits on silicon FET scaling. This is one of the main reasons for the increased interest in post-silicon technologies.
Question 4: There has recently been a surge of interest in memristors. Is this interest justified?
Answer: Memristors have been researched for quite a while, and they do hold promise in the memory area. It isn’t clear if memristors are suitable for logic, which is the NRI’s primary focus, since memristors operate slower than silicon transistors. But slow switching speed is actually a serious problem for many post-CMOS technologies – they often operate at a fraction of the speed of silicon FETs.
Question 5: Is graphene currently the front-runner in the race to supplant silicon? Is it considered a more suitable candidate than carbon nanotubes?
Answer: Graphene is currently one of the materials we are focusing on, and it does have a number of advantages. It has very high switching speed, and it should be feasible to fabricate graphene FETs. Even more interesting for NRI post-FET switch research is the unique physics in graphene that could lead to completely new devices based on pseudospintronics or other state variables. So a hybrid chip containing both silicon and graphene is a real possibility.
Question 6: When will the first logic gate based on one of these nanoelectronics technologies emerge?
Answer: We have already seen individual switches made from flakes of graphene. At some point there should be a breakthrough – some researcher will figure out how to make a uniform layer of graphene across a wafer. That should hopefully happen within the next couple of years, and we will need it to happen within that time frame if we are to have working products by 2020.
Question 7: What about nanotubes?
Answer: Nanotubes could make excellent FETs, and could probably be used for a generation or two. But since these would still be charge-based devices, they would not allow for an entirely new scaling path.
Question 8: What is your assessment of spintronics?
Answer: Whereas charge-based devices take advantage of an electrons charge, spin-based devices determine whether an electron’s “spin” is up or down. The primary advantages of spin-based devices are that they can be non-volatile, so can consume little power and dissipate minimal heat. Spin or magnetic devices could also potentially be used as multi-bit devices, which might compensate for low switching speeds. Switching speeds are a problem for logic applications in particular, since spintronics is currently substantially slower than FETs, which is why spin and magnetic have mostly been looked at for memory and storage up to now.
Question 9: Any post-CMOS technology will need to first integrate with CMOS processes. How will these manufacturing challenges be surmounted?
Answer: The manufacturing challenges will be huge for any new devices. We assume that new devices will initially integrate with CMOS. Obviously any such components would need to withstand the harsh chemical processes that are employed in chipmaking fabs. Perhaps we could put components on top of chips, or use some 3D technology.
Question 10: What organizations fund the NRI?
Answer: There are three components to our funding. The first component comes from semiconductor corporations IBM, Intel, GLOBAL FOUNDRIES, Micron and Texas Instruments. The second component comes from NIST and the NSF. The third component comes from state governments. So we have centers in New York, California, Texas and Indiana, and these research centers are located in these locations because state governments provided matching funds.
Question 11: Does the SRC or NRI have a roadmap?
Answer: The SRC uses the International Technology Roadmap for Semiconductors (ITRS) roadmap to ascertain what technologies need to be researched. So the SRC tracks the ITRS roadmap closely. The NRI does not have any particular roadmap that we follow, since we don’t yet know what technology will eventually supplant silicon CMOS, but use the ITRS roadmap as a guide know where CMOS will be in the future, and hence the bar we must reach to surpass it.
Question 12: How big are the potential gains of post-silicon computing? Are orders of magnitude speedup feasible?
Answer: Although we don’t have any specific performance goals in mind, orders of magnitude speedups should be feasible. Any new technology that requires a major manufacturing change would need to be at least an order of magnitude better than conventional technology in order to justify the expense.
Question 13: What computing technology excites you the most?
Answer I am most excited about the potential of graphene. The properties of graphene, which is essentially a single sheet of pure carbon, are pretty amazing. Graphene has an extremely high electron mobility and thermal conductivity. Graphene transistors have also already been fabricated, so it could be used to substantially increase transistor speeds for charge-based devices. Or it could form the basis of an entirely new computing paradigm, such as spintronics. The technology is improving exponentially and allows the industry to hedge its bets.
Question 14: When do you see the exponential growth in computing ending?
Answer: If these technologies pan out, performance doublings could continue into the 2030s. This computing industry has always been searching for ways to increase computations per second.. As long as the computer industry exists it will incessantly endeavor to increase speeds. Although at some point scaling has to end, I predict that increasing functional throughput will continue for at least the next quarter century.