EETimes reports Toshiba Corp. has said it has developed a photoresist suitable for use with extreme ultraviolet (EUV) lithography and proved its viability in the world's first 20-nm generation process technology.
Extreme UV Lithography
During this year’s EUVL Symposium, steady progress was reported for EUVL including:
Experts from Cymer reported laser produced plasma (LPP) sources generate 50 watts at intermediate focus (IF). This compares with a system requirement of 180 watts needed to expose 100 wafers per-hour in high-volume manufacturing.
SEMATECH researchers and research partners highlighted the key role the consortium has played in achieving significant advances in EUV resists, specifically through achieving 20 nm resist resolution images for chemically amplified resists and addressing the challenges of simultaneously meeting resolution, line edge roughness (LER), and sensitivity targets in a systematic way.
With EUVL moving closer to pilot line introduction, mask yield has become a critical focus and several chip manufacturers as well as consortia are using wafer printing and/or actinic aerial image review to characterize mask defects. Those printability studies show that the number of printing mask blank defects increases with decreasing feature size. About 50 percent of all inspected mask defects – mask blank defects, absorber defects, and pattern defects - print at the wafer level.
Lastly, the EUVL Symposium Steering Committee identified at the conclusion of the conference three remaining focus areas that the industry needs to work on to enable EUVL manufacturing insertion:
1. Availability of defect-free masks, throughout a mask lifecycle, and the need to address critical mask infrastructure tool gaps, specifically in the defect inspection and defect review area
2. Long-term source operation with 100 W at the IF and 5 megajoule per day
3. Simultaneous resist resolution, sensitivity, and LER
Key progress indicators outlined at the Immersion Extensions Symposium, include the following:
Immersion lithography has been extended to the 22 nm using a variety of approaches.
A wide variety of techniques including spacer, double etch, resist freezing processes, litho etch-litho etch, and source mask optimization were all demonstrated as viable double patterning approaches.
Invited speaker David Medeiros, of IBM, emphasized the explosion of masking at 22 nm using double patterning in his presentation entitled “Lithography on the Edge.” Sam Sivakumar of Intel predicted that future lithography processes will combine multiple approaches rather than a single winning technique in his presentation entitled “Technical and Manufacturing Challenges and the Prospect for HVM using ArF Pitch Division.”
Although progress is being made towards enabling the 22 nm node, the conference highlight was that the cost of ownership is of greater importance than the technical solution itself.