A new type of nanowire that can be fabricated using conventional manufacturing techniques has been reported by researchers from the A*STAR Institute of Microelectronics and the Institute of Materials Research and Engineering in collaboration with colleagues from the National University of Singapore1. The key to their success is a core/shell structure in which a silicon–germanium core is sheathed by a silicon outer layer to form the nanowire.
The research team showed that the composite nanowires perform better in transistor structures than silicon alone. Silicon and germanium combined have better charge-carrier mobility than silicon, although the many charge-carrier traps that form at the interfaces between the different materials in silicon–germanium transistors have previously made it difficult to exploit this advantage. To avoid this problem, the researchers added an outer coating of silicon to the nanowires .
The core/shell nanowires were created using vacuum-deposition techniques that are fully compatible with current methods for the industrial fabrication of transistors. Importantly, the researchers used bulk silicon substrates, which are much cheaper and more readily available than the more specialized silicon-on-oxide substrates used previously for the fabrication of silicon–germanium transistors. The different layers are deposited and shaped using patterning and etching techniques, with the 12 nm-wide silicon–germanium core and 4 nm-thick silicon shell formed directly on the substrate.
The silicon–germanium nanowire transistors compared very well with silicon-only devices fabricated using the same process. The drive currents achievable by the transistors containing germanium were higher by 15%. The researchers attributed this improvement to the compressive strain in the nanowires caused by their position in the devices, which modifies their electronic structure. The intrinsically higher charge mobility in silicon–germanium also plays a part. “It would be difficult to decouple the two effects,” says Dim-Lee Kwong, one of the A*STAR members on the research team.
The researchers also found evidence of two types of conduction. When the gate voltage—the voltage that controls the amount of current flowing through the device—is low, conduction occurs through the silicon–germanium core alone as a result of quantum well formation in the core due to the smaller band gap of silicon–germanium compared to silicon. At higher gate voltages, with inversion at the wire surface, a combined conduction from both the silicon shell and the quantum well of the silicon–germanium core is observed, Kwong explains.
“The achievement of our transistors on bulk silicon instead of silicon-on-oxide is expected to carry the additional advantage of better heat dissipation,” says Kwong. “In the future, further improvements in the performance are expected by increasing the germanium concentration in the silicon–germanium core.”
We demonstrated, for the first time, p-MOSFETs (LG ges 40 nm) with SiGe/Si core/shell channel integrated on bulk Si using a CMOS-compatible top-down processes. The Omega-shaped nanowire (NW)-like channels comprised of ~12-nm-thick inner SiGe core and 4-nm-thick outer Si shell. The devices exhibited good subthreshold characteristics (with SS ~128 mV/dec), suggesting successful surface passivation of the SiGe NW body by the outer Si capping layer. Drive currents of ~167 muA/mum is achieved, which is 15% enhancement over the reference Si-channel devices fabricated by the same process. Double gm peaks are observed at low drain bias for the core/shell SiGe NW devices, confirming the quantum confinement of holes in the SiGe inner core.