Intel hoped to use EUV at 22-nm, which is due out in 2011. The problem is that EUV will not be ready in time for 22- or 15-nm in production–at least at Intel, said Intel senior fellow Yan Borodovsky, director of advanced lithography in the company’s Technology and Manufacturing Group.
* 193-nm immersion with pitch division is the only option for high-volume manufacturing at 15-nm (for 2013)
* there will be pilot line production with EUV at 15nm
* at 11-nm, Intel is also looking at 193-nm immersion, with a quint–or five mask–patterning (there is currently double and triple lithography)
* To get implemented at Intel, EUV must prove that it works by 2011 or 2012. Maskless must prove viable and that it works by 2012.
* Nikon has devised a new lens for its latest 193-nm immersion scanner and revised its roadmap for extreme ultraviolet (EUV) lithography.
* Officials from Nikon also confirmed that EUV is delayed for the 22-nm ”half-pitch” node. EUV will be ready for the 16-nm node
* 193-nm immersion tool called the NSR-S620D. The tool features a lens with a numerical aperture (NA) of 1.35 (improved from first version 1.30)
* a new platform, dubbed the Streamlign. Overlay is 2-nm and throughput is 200 wafers an hour
* Nikon is working on an EUV tool with a six-mirror, 0.35 NA lens. That tool is due out in 2012. In parallel, Nikon is working on a tool with an NA of 0.4, which can extend to 16- and 11-nm chip production. That tool is due out in 2014 or 2015.
The breakthrough is based on a control gate around a silicon wire that measures just a few dozen atoms in diameter. The gate can be used the squeeze the electron channel to nothing without the use of junctions or doping. The development, which could simplify manufacturing of transistors at around the 10-nanometer era, was created a by a team led by Professor Jean-Pierre Colinge and a paper on the development has been published in Nature Nanotechnology.
It simplifies the production of transistors which also have a near-ideal sub-threshold slope, extremely low leakage currents and less degradation of mobility with gate voltage and temperature than classical transistors, the researchers have claimed. Nonetheless such device can be made to have CMOS compatibility.
The general problem with double-patterning is cost. In simple terms, the mask must be exposed twice in double-patterning. It is 2.5 times more expensive than current 193-nm immersion, due to the added process steps.
Samsung and others want EUV, which, in theory, brings single-exposure back into play, thereby lowering cost. And, in fact, Samsung has recently jumped on the EUV bandwagon–and for good reason: EUV is the best lithography option for the production of devices at the 20-nm ”half-pitch” node and below.
EUV still needs defect free masks, power source 5 to 6 times more powerful than those available now and resists.