Junctionless transistors could be implemented commercially at around the 20-nm manufacturing node. The junctionless transistor scales far better than a conventional transistor which will need to implant and control complex dopant gradients and profiles in diminishing distances. “The junctionless device does scale better. You still need the high resolution etching but you don’t have to scale the gate oxide as aggressively as you do on a regular device” Professor Colinge said.
The junctionless transistor is based on use of control gate around a silicon nanowire. The gate can be used to modulate the resistance of the nanowire and to “squeeze” the electron channel to nothing, thus turning off the device. Doping is used to produce p- and n-type FETs but there are no steep dopant gradients nor junctions, which promises simplified manufacturing.
Such a major change in the structure of the fundamental electronic device could be expected to require a great deal of independent research. An introduction at or around 20-nm would require companies to switch more or less immediately. However, a switch to the junctionless transistor could fit in with previously forecast moves by the industry away from planar transistors and towards FinFETs and multi- and wrap-around gate structures.
Speaking to EE Times by telephone Professor Colinge said: “It’s not shown in the Nature paper but we have made a silicon nanowire measuring about 10 nanometers by 10 nanometers. Now there is a rule of thumb that the gate length should be about twice the nanowire dimensions to avoid short channel effects. I think junctionless transistors could intersect with ITRS [International Technology Roadmap for Semiconductors] at 20-nm.”
Professor Colinge continued: “The junctionless transistor could compete now but it will take time for semiconductor companies to get used to the idea. People are scared of the high doping levels.”
Dopant levels of between 2 x 10^19 and 5 x 10^19 atoms per cubic centimeter were used. The high doping levels are required to ensure a high current drive and good source and drain contact resistance.
All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult fabrication challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.