The push for 3-D is because of problems with regular scaling of chips to smaller dimensions, so they are looking to do more stacking and connecting.
At the 2011 GSA Memory Conference here on Thursday (March 31), four industry organizations-IMEC, ITRI, Sematech and SEMI-separately made presentations about the latest progress within their respective entities for 3-D chips based on TSV.
A 3-D working group within SEMI met for the first time this week to sketch out the initial wafer and tool standards for TSV technology. SEMI has three task groups within its 3-D group. A fourth group is being formed, which may be led by Applied Materials Inc.
In a separate program within Sematech, the chip-making consortium is expanding its own 3-D program. One surprising chip maker, Analog Devices Inc., is joining Sematech’s ”3-D Design Enablement Center.’’ Altera, LSI, On Semiconductor and Qualcomm are also part of the center.
A plethora of others are also scrambling to develop TSV-based technology-and for good reason: There are fears that IC scaling is becoming too costly for most chip makers-or will end in the distant future.
So instead of scaling, there is another concept on the table: stack and connect devices in a 3-D configuration using TSVs. For years, chip makers have been talking about 3-D chips based on TSVs. But except for select products-such as CMOS image sensors-the technology has not moved into the mainstream, due to costs, lack of standards and other factors.
One of the problems with TSV (through silicon via) is the lack of standards. In December, SEMI moved to reverse the problem by forming the Three-Dimensional Stacked Integrated Circuits (3DS-IC) Standards Committee.
Right now, there are several new and mainstream 3-D chip projects in the works. For example, Semtech Corp. is working with IBM Corp. and its 3-D TSV technology to develop a combination analog-to-digital converter and DSP platform. These two different technologies are connected through a single wiring layer on an interposer, which supports a bandwidth of greater than 1.3-Tbps.
In a separate effort, Hynix, Samsung and others have identified a new device vehicle that could propel TSV-based 3-D chips into the mainstream: a wide I/O DRAM for cell phones, tablets and related products.
Wide I/O, a memory interface standard in review at JEDEC, defines a 512-bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8- gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions.
Today, mobile DRAM is based on a technology called low-power double data rate 2 (LPDDR2). Beyond LPDDR2, Samsung and others are pushing wide I/O DRAM for mobile applications. Wide I/O will evolve in two phases. The first wide I/O DRAMs are four-partitioned devices, which will be stitched together via micobumps. They are expected to appear in 2013.
In the future, vendors hope to stack multiple wide I/O DRAMs using TSVs. Some say those devices will appear in 2014 or 2015. Some believe the technology will appear later than sooner.
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Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
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