Tabula Spacetime device reconfigures on the fly at multi-GHz rates, executing each portion of a design in an automatically defined sequence of steps. Although manufactured using a standard CMOS process, Spacetime uses this ultra-rapid reconfiguration to make Time a third dimension, resulting in a 3D device with multiple layers or folds in which computation and signal transmission can occur. Each fold performs a portion of the desired function and stores the result in place. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function. By rapidly reconfiguring to execute different portions of each function, a 3D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an inherently 2D FPGA. A designer can realize all of the benefits of 3D within a familiar methodology using the Spacetime compiler that automatically maps standard RTL into Spacetime.
Spacetime devices will provide significantly higher logic, memory and signal processing capabilities than FPGAs, and their much higher density makes them suitable for volume production.
MIT Technology Review – The new chips—made by a startup called Tabula—are a cheaper, more powerful competitor to an existing type of reprogrammable chip known as a field programmable gate array (FPGA). FPGAs are sometimes shipped in finished devices when that is cheaper than building a new chip from scratch—usually things that are expensive and sell in low volumes such as CT scanners. More commonly, FPGAs simply provide a way to prototype a design before making a conventional fixed microchip.
If programmable chips were more powerful, and less costly they could be used in more devices, in more creative ways, says Steve Teig, founder and chief technology officer of Tabula. His company’s reprogrammable design is considerably smaller than that of an FPGA. “FPGAs are very expensive because they are large pieces of silicon,” says Teig, “and silicon [wafer] costs roughly $1 billion an acre.” The time it takes for signals to traverse the relatively large surface of an FPGA also limits its performance, he says.
“It’s like being inside a very large, one story building—the miles of corridors slow you down,” he says. As with a building, stacking layers of circuit on top of each other helps, by providing a shortcut between floors, says Teig. But unfortunately, the technology needed to build stacked, 3-D chips is still restricted to research labs. Instead Teig found a way to make a chip with just one level behave as if it were eight different ones stacked up.
Imagine you walked into the elevator in a building and then walked back out, and that I rearranged the furniture quickly while you were in there,” says Teig. “You would have no way to tell you weren’t on a different floor.” Tabula’s chips perform the same trick on the data they process, cycling between up to eight different layouts at up to 1.6 billion times per second (1.6 Gigahertz). Signals on the chip encounter those different designs in turn, as if they were hopping up a level onto a different chip entirely. “From its behavior, our [design] is indistinguishable from a stack of chips,” says Teig, who calls the virtual chip layers “folds.”
Making the reconfigurable approach cheaper could enable even consumer electronics to ship with programmable chips, making it possible for them to be upgraded with new design tweaks. That approach is currently used only in some expensive equipment such as cell-phone base stations. “Sony could say, ‘look at what our competitor Toshiba did’, and upgrade the chips inside their TVs to provide new features,” says Teig. “Getting to digital cameras or TVs is definitely within reach.”
However, Rich Wawzyrniak, who tracks FPGAs and related technology for analyst firm Semico Research, points out that there are limitations to this approach. “The power consumption if these devices is relatively high, and likely too much for a device like a phone,” he says.
But ultimately, says DeHon, reconfigurable chips should morph their design even more often, shifting their workings to match the task in hand in a blend of software and hardware. “These things are really platforms that can run any computation. The grand vision is that we come up with a way for a program’s code to be mapped to the chip when it runs.”