IMEC to detail memristor progress at VLSI Symposia

EETimes – IMEC (Leuven, Belgium), claims RRAM will be ready for reliable mass production below 20 nanometers, will describe its cross-bar architecture. IMEC claims the architecture is denser, faster and lower-power than flash, but suitable to replace any memory type, including DRAMs.

IMEC and other research groups backing variations of the memristor claim that, in the future, a single universal memory technology will replace flash memory and all vintages of random-access memories. The memristor was invented by by professor Leon Chua at the University of California-Berkeley and has been championed by Hewlett-Packard Co.

“HP is using the term memristor to describe a device which has certain I-V characteristics,” said Malgorzata Jurczak, program manager memory devices at IMEC. “But such I-V characteristics are typical to any RRAM cell using oxygen vacancy migration in transition metal oxide.”

IMEC is saying that memristors are just a type of RRAM.

IMEC’s resistive random access memory (RRAM) sandwiches hafnium-oxide memristive material between metal electrodes.

HP is sandwiching titanium-oxides in its memristive crossbar arrays, but at VLSI Symposia IMEC will describe using hafnium-oxide and other formulations for its RRAMs. In addition, there are two different ways of performing the resistive switching, using interfacial modification where oxygen vacancies are migrated either towards or away from the interface, thus modulating the tunneling barrier between the electrode and the conductive part of the oxide. Alternatively, filamentary switching aligns the oxygen vacancies in a conduction path which can be ruptured or established by oxygen vacancy migration. Either way, the advantage is the same—ultra-high density cross-bar arrays that use programming voltages to migrate oxygen vacancies, thereby changing the resistance of the bit-cell in a non-volatile manner.

“HP is claiming to using interfacial type of switching,” said Jurczak. “But in our papers we are using filamentary switching.”

IMEC will report that it has achieved ultra-fast sub-nanosecond programming times and ultra-low power sub-500 nanoamp operating currents using filamentary switching. IMEC will also report improved bit-cell reliability by virtue of its sophisticated materials stack engineering.

“We are overcoming the scaling limitations of conventional flash memory cells,” said Jurczak. “Major memory players joined our research program on emerging memory technologies, proving the value of our RRAM research to the global industry.”

Summary titles of IMEC’s four papers are: “Dynamic ‘Hour Glass’ Model for Set and Reset in Hafnium Oxide RRAM,” “Ultralow sub-500nA Operating Current in High-Performance Bipolar RRAM Achieved Through Understanding-Based Stack-Engineering,” “Process-Improved RRAM Cell Performance and Reliability and Paving the Way for Manufacturability and Scalability for High Density Memory Application,” and “Field-Driven Ultrafast sub-ns RRAM Programming.”

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