1. ZDNet – At IEDM, the main attraction this year is a talk by Intel on 22nm SoC technology using its 3-D transistors, generally known as FinFETs, for mobile processors. Intel’s Ivy Bridge Core processors for laptops, desktops and servers already use this technology, but this will be the first time the company has talked in detail about how its 22nm technology with FinFETs will translate to Atom mobile processors for the increasingly important smartphone and tablet markets. Intel’s current Atom processors are still stuck on the older 32nm planar technology, but in mobile the company has set an aggressive goal of shrinking its chips once a year. Although it is still playing catch-up to a host of ARM competitors, Intel insists that ultimately the best transistor will win, and this presentation may be the first indication of whether it can really deliver on this.
Intel isn’t the only one working on FinFETs. The leading-edge foundries are racing to be the first to offer them to fabless customers like Qualcomm and Nvidia. At IEDM, TSMC, the world’s largest foundry, will talk about a FinFET solution using a different channel material, but it isn’t clear when (or if) this might be used in production. We do know that TSMC will rely on a conventional planar recipe at the next node, 20nm, but shortly afterwards it is planning to release a 16nm process with FinFETs. Meanwhile GlobalFoundries says its first process with FinFETs, dubbed 14XM, will be available for testing next year and in production by 2014, yet the company is not scheduled to present its FinFET technology (though Suresh Venkatesan, the foundry’s Senior Vice President of Technology Development will moderate a panel on the future of FinFETs).
The alternative to FinFETs at 22nm and below is a technology called fully-deleted SOI (FD-SOI), which is manufactured using a different type of wafer known as Silicon-On-Insulator. IBM, STMicroelectronics, GlobalFoundries and others will talk about their progress on FD-SOI, which is considered a good candidate for low-power mobile processors. IBM will also give details on the upcoming 22nm generation of its standard SOI process for high-performance chips such as the Power processors used in servers and game consoles.
Both FinFETs and FD-SOI are likely to extend silicon for the next several generations, but as usual there will be many sessions on what happens when these solutions run out of steam. Intel researchers will give a talk on the technologies for the “ultimate CMOS device” and discuss the candidate for eventually replacing CMOS. And there will be many papers on the progress with these candidates including new channel materials, nanowires and nanotubes, graphene and spintronics.
As scaling grows more difficult, and requires increasingly exotic materials and structures, there has been a lot of debate about whether the foundries that manufacture chips for fabless companies will be able to keep up with Intel. Earlier this year Intel’s Mark Bohr said the foundry model was “collapsing.” Ajit Manocha, the CEO of GlobalFoundries, said that “many of us really got our feathers ruffled” by those comments, and at IEDM, he’ll present the case for why foundries are here to stay.
The other big topic at IEDM is memory, and in particular whether any emerging memory technology is poised to replace NAND flash memory for storage. The short answer, as always, is no. But there is lots of interesting work going on.
Everspin recently announced it will be the first to commercialize an ST-MRAM (Spin-Torque Magnetoresistive RAM). The initial 64Mb device, which Everspin will discuss at IEDM, is intended as a buffer in solid-state drives and storage arrays, but as the density increases ST-MRAM could become a replacement for DRAM. Toshiba will also be pitching a form of MRAM as an alternative for the cache on mobile processors to reduce power.
The most likely replacement for NAND flash, however, continues to be 3D stacked flash memory. Micron and Intel, SK Hynix and Macronix will all talk about their work on 3D NAND.
Neuromorphic–or brain-like–electronic systems that mimic cognitive functions are the focus of research because of their potential for complex tasks such as pattern-recognition. A technical presentation by a team from Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated something called spike-timing-dependent plasticity (STDP). STDP is an electronic analog of a brain mechanism for learning and memory, so an electronic system that accurately performs STDP can be said to be “learning.” The 1-Kb RRAM array has a simple crosspoint structure and possibly can be scaled to 4F, the theoretical minimum size for a crosspoint array.
A team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses.”
A Massachusetts Institute of Technology research team has found a way to release, or remove, MEMS devices from a substrate after fabrication so that they can be integrated with CMOS. They did this by driving a MEMS resonator electrostatically using deep trenches that functioned as capacitors. The resonator frequency could be tailored easily via the lithography used to build the trenches, and the trenches also served as acoustic Bragg reflectors to confine and localize the resonance vibrations. The devices were built using a 32-nm SOI process. The 3.3-GHz MEMS resonator had a figure of merit (Q) of 2057, the highest reported to date for an unreleased MEMS resonator, according to the researchers. They claim this work paves the way for high-Q, multi-frequency sources to be built and intimately integrated in CMOS with no need for additional processing or packaging
MIT’s deep-trench work paves the way for high-Q, multi-frequency sources to be built and intimately integrated in CMOS with no need for additional processing or packaging.
IBM researchers will demonstrate high-performance state-of-the-art CMOS circuits —including SRAM memory and ring oscillators—on a flexible plastic substrate. IBM built extremely thin silicon on insulator (ETSOI) devices with a body thickness of just 60 angstroms. They used controlled spalling, a simple, low-cost room-temperature process, which flakes off the silicon substrate. The devices with gate lengths of less than 30 nm and a gate pitch of 100 nm were transferred to a flexible plastic tape. The ring oscillators had a stage delay of 16 ps at 0.9 V, believed to be the best reported performance for a flexible circuit, according to the researchers. A slight degradation of delay for the flexible sample after the layer transfer comes from degradation of p-FET performance due to strain effects.
Molybdenum Sulfide (MoS) is competing with graphene to be the next big thing after silicon. Possessing some characteristics similar to graphene, MoS also claims a wide energy bandgap, enabling transistors and circuits to be built from it directly. An M.I.T.-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter).