Gate-All-Around Transistors: In a new design, the transistor channel is made up of an array of vertical nanowires. The gate surrounds all the nanowires, which improves its ability to control the flow of current. Platinum-based source and drain contacts sit at the top and bottom of the nanowires.
Engineers may already have come up with the technology that will fend off the Moore Law is doomed skeptics: nanowire FETs (field-effect transistors).
In these nanodevices, current flows through the nanowire or is pinched off under the control of the voltage on the gate electrode, which surrounds the nanowire. Hence, nanowire FETs’ other name: “gate-all-around” transistors. However, because of their small size, single nanowires can’t carry enough current to make an efficient transistor.
The solution, recent research shows, is to make a transistor that consists of a small forest of nanowires that are under the control of the same gate and so act as a single transistor. For example, researchers at Hokkaido University and from the Japan Science and Technology Agency reported last year in Nature a gate-all-around nanowire transistor consisting of 10 vertical indium gallium arsenide nanowires grown on a silicon substrate. Although the device’s electrical properties were good, the gate length—a critical dimension—was 200 nanometers, much too large for the tiny transistors needed to power the microprocessors of the 2020s.
Now two researchers working in France, Guilhem Larrieu of the Laboratory for Analysis and Architecture of Systems, in Toulouse, and Xiang‑Lei Han of the Institute for Electronics, Microelectronics, and Nanotechnology, in Lille, report the creation of a nanowire transistor that could be scaled down to do the job. It consists of an array of 225 doped-silicon nanowires, each 30 nm wide and 200 nm tall, vertically linking the two platinum contact planes that form the source and drain of the transistor. Besides their narrowness, what’s new is the gate: A single 14-nm-thick chromium layer surrounds each nanowire midway up its length.
ABSTRACT – Nanowire-based field-effect transistors are among the most promising means of overcoming the limits of today’s planar silicon electronic devices, in part because of their suitability for gate-all-around architectures, which provide perfect electrostatic control and facilitate further reductions in “ultimate” transistor size while maintaining low leakage currents. However, an architecture combining a scalable and reproducible structure with good electrical performance has yet to be demonstrated. Here, we report a high performance field-effect transistor implemented on massively parallel dense vertical nanowire arrays with silicided source/drain contacts and scaled metallic gate length fabricated using a simple process. The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography. These benefits are important in the large-scale manufacture of low-power transistors and memory devices.
“The advantage of an all-around gate allows the creation of shorter gates, without loss of control on the current through the channel,” explains Larrieu. “We demonstrated the first vertical nanowire transistor with such a short gate.” An all-around gate will be a must if gate lengths are to get smaller than 10 nm, he says. In that scheme, “the size of the gate depends only on the thickness of the deposited layer; there is no complicated lithography involved,” he adds.
The nanowires were of an unusual construction. Unlike with most vertical nanowire transistor prototypes, in which the nano wires are grown upward from a substrate, the French duo created their nanowires by starting out with a block of doped silicon and then etching away material to leave nano pillars. In between the pillars, they deposited an insulating layer to about half the pillars’ height. Then they deposited the 14 nm of chromium and filled the remaining space with another insulating layer. “We tried to make the process completely compatible with current technology used in electronics. No new machines will have to be invented,” says Larrieu. The researchers have plans to try to go below 10-nm gate length, and also to use indium gallium arsenide nanowires because of the better electron mobility.
According to Judy Hoyt, a researcher at the Microsystems Technology Laboratories at MIT, gate-all-around technology is now under study at a number of university labs worldwide. But as the nanowire transistors are more complex than the FinFETs, will this effort allow Moore’s Law to live longer and fit even more transistors on a chip? “The jury is still out,” says Hoyt. It depends on what the fabrication process and the structure will be, she says. “You really have to get the physics right, and that is what all these efforts are based on.”