Scientists have developed a new type of graphene-based transistor and using modelling they have demonstrated that it has ultralow power consumption compared with other similar transistor device. They could eventually achieve 100 gigahertz clock speeds.
Building transistors that are capable of switching at low voltages (less than 0.5 volts) is one of the greatest challenges of modern electronics. Tunnel transistors are the most promising candidates to solve this problem. Unlike in conventional transistors, where electrons “jump” through the energy barrier, in tunnel transistors the electrons “filter” through the barrier due to the quantum tunneling effect. However, in most semiconductors the tunneling current is very small and this prevents transistors that are based on these materials from being used in real circuits.
In a continuous search for the energy-efficient electronic switches, a great attention is focused on tunnel field-effect transistors (TFETs) demonstrating an abrupt dependence of the source-drain current on the gate voltage. Among all TFETs, those based on one-dimensional (1D) semiconductors exhibit the steepest current switching due to the singular density of states near the band edges, though the current in 1D structures is pretty low. In this paper, we propose a TFET based on 2D graphene bilayer which demonstrates a record steep subthreshold slope enabled by van Hove singularities in the density of states near the edges of conduction and valence bands. Our simulations show the accessibility of 35,000 ON/OFF current ratio with 150 mV gate voltage swing, and a maximum subthreshold slope of (20 μV/dec)^−1 just above the threshold. The high ON-state current of 0.8 mA / μm is enabled by a narrow (~0.3 eV) extrinsic band gap, while the smallness of the leakage current is due to an all-electrical doping of the source and drain contacts which suppresses the band tailing and trap-assisted tunneling.
(A) Layout of the proposed graphene bilayer TFET with electrically defined source and drain regions (B) Band diagram of graphene bilayer TFET for the optimal biasing conditions. At zero top gate bias, VG = 0, the TFET is switched on, while at VG less than 0 it is switched off.
SOURCES- MIPT, Nature Scientific Reports