Professor Qian acknowledged that despite export restrictions on processor and software technology imposed by the US, work continues on two 100 petaflops (peak) systems: the next iteration of Tianhe-2, installed at the National Supercomputer Center in Guangzhou, and the upcoming Sunway system coming to the Jiangnan Institute of Computer Technology in Wuxi, China, near Shanghai. The official line is that these systems will be ready “by the end of the year,” but there have been rumblings that one or both of these systems will be introduced during the ISC’16 event in June.
The second 100 petaflops system (Sunway) will use the next-generation Chinese-made ShenWei chips and will be implemented together with a general purpose cluster system of 1 petaflops performance. This configuration is designed to meet a wide variety of application requirements.
Professor Qian provided an overview of China’s main weaknesses, the most significant being a gap in kernel technologies and the lack of a suitable accelerator for the Tienhe-2 upgrade on account of the US embargo. “Currently there is no available accelerator to upgrade the system and it’s a major issue from the point of view of the Chinese government,” he said. “We had to change our plan and rely on our own processors. We are in urgent need for the system software, for the domestic processor, for the tool software and also the application software. Without an ecosystem around the domestic processors, we will not succeed in this respect.”
At the ISC high performance conference, there will be a talk The New Sunway Supercomputer System at Wuxi on Tuesday, June 21, 2016
13th Five-Year Plan Targets Exascale
After updating the continued supercomputing progress being made under the 12th five-year plan, Qian walked through brand-new elements of China’s 13th five-year plan, which puts into motion one of the most ambitious exascale programs in the world. If successful the program will stand up an exaflops (peak) supercomputer by the end of 2020 within a 35 MW power limit.
China is in the midst of overhauling its national research system and restructuring 100 programs into five tracks: Basic research program; mega-research program; key research and development program; enterprise-oriented research program; research centers and talents program.
The new track that is being focused on in the session is the third one – the key research and development program. A proposal for the track-3 key project on HPC was submitted in September 2015 and launched on February 2016.
The primary pillars for the key project are developing exascale computers, promoting computer industry by technology transfer and a China-controlled HPC technology set. The major tasks are next-generation supercomputing development, CNGrid upgrading and transformation, and domain HPC applications development. A robust supercomputing program is seen as a critical for addressing grand challenge problems spanning the environment, energy, climate, medicine, industry and science.
According to Professor Qian, the number one priority task is the development of an exascale supercomputer, based on a multi-objective optimized architecture that balances performance, energy consumption programmability, reliability and cost.
To achieve this goal [exaFLOP supercomputer], China is funding research into novel high performance interconnects with 3-D chip packaging, silicon photonics and on-chip networks. Programming models for heterogeneous computers will emphasize ease in writing programs and exploitation of performance of the heterogeneous architectures.
The program includes the development of prototype systems for verification of the exascale computer technologies. The computer scientists will explore possible exascale computer architectures, interconnects which can support more than 10,000 nodes, and energy efficiency technologies, as power demand is known to be one of the biggest obstacles toward exascale.
The exascale prototype will be about 512 nodes, offering 5-10 teraflops-per-node, 10-20 Gflops per watt, point to point bandwidth greater than 200 Gbps. MPI latency should be less than 1.5 us, said Qian.
SOURCE- HPCWire, ISC