BeSang's claim to fame since its inception, has been its ability to build 3D chip monolithically with all control logic on the bottom layer, leaving the entire top area for vertical memory cells (both of which can be stacked). Competitive 3D NAND bit cells use up to 31,000 square nanometers per bit, due to using about 60 percent of the cell for three functions: control logic (34 percent), a tungsten isolation slit (20 percent) and a word-line staircase (26 percent). On the other hand, BeSang's monolithic process can fit 30 NAND bits into the same area, according to the company, thus accounting for their cheaper price-per-bit.
Besides bigger cells, 3D NAND from Samsung and others use a difficult to implement staircase word-line architecture that extends about 20 microns for Samsung's 32-layer 3-D NAND or 40 microns for its proposed 64-layer 3D NAND, according to BeSang. The result is not only lower bits per square micron, but also longer wafer processing time due to the multiple staircase etching and contact forming steps.
"With just five masks, we can process our 3D NAND with three-times the capacity of SanDisk's or Samsung's designs in just five days processing, whereas it takes them as much as 10 weeks to process their 3D NAND chips," said Lee. "The capital equipment we need also costs as much as 10-times less than theirs."
3D inCities has a detailed comparison of BeSang 3D super NAND against regular 3D NAND
SOURCES- BeSang, EEtimes, 3Dincities