Smart, connected devices, and the IoT ecosystem they are helping to create, promise to transform everyday life. For individual consumers that might mean making devices more efficient and cost effective for their daily tasks, keeping them safer, or even helping ensure they live healthier lives. For businesses, the IoT promises significant advantages in terms of automation, energy efficiency, asset tracking and inventory control, shipping and location, security, individual tracking, and energy conservation.
But to reach the tens of billions of devices projected to make up the IoT, designers will have to overcome significant implementation challenges. Some of the key among them will be making IoT devices power efficient, handling incompatible interfaces, and providing a processing growth path to handle the inevitable increase in device performance requirements. An FPGA-based design approach can help address such challenges.
Challenge 1 – Power Efficiency
The IoT is a powerful concept with capabilities promising to literally transform the way society lives and works. In fact, development is currently underway in a variety of areas that will make many things look very different than they are today—and not just from a consumer perspective. Consider, for example, that wearable devices like the Nike FuelBand often require eight or nine components such as the processor, the wireless module, memory, a display, eight sensors, and a USB interface. Over the next few years, component counts may drop, but the complexity and transistor count of the three or four remaining components will grow rapidly as more memory and processing power is required, and as screen resolutions and brightness increase. Achieving an energy efficiency that will enable IoT devices to run for years on a single battery will not be an easy task. It demands the use of low-power components and more efficient power systems. And, it will require changes at both the architectural and silicon level.
One approach provides “always-on” solutions using a small, low-power FPGA to monitor sensors, buttons, or even voice commands. The processors, wireless modules, and displays can be left in a standby mode until the FPGA determines the user’s need to “wake-up” the terminal and provide service. In addition to low power, this architecture enables modal state power management with some granularity on what mode the device is actually in—is it on or off, is it sleeping or partially awake—allowing it to dynamically go from one phase to another. This approach offers significant power savings, resulting in longer battery life, longer display lifetime, and lower thermal radiation.
Challenge 2 – Incompatible Interfaces
Very small, low cost FPGAs can be used to bridge interfaces.
Challenge 3 – Migration to a New Processor Due to Increased Requirements
A processor companion FPGA. A low cost FPGA can be used to augment and supplement many of the processor’s requirements, allowing the designer to keep the existing processor and minimize the impact to the firmware