Hewlett-Packard researchers have designed a faster, more energy-efficient chip by packing in more transistors–without shrinking them. Instead of using aluminum wiring that take up a lot of space beside transistors, they used crossbar nanowire mesh that goes on top to connect the transistors. HP’s design has the potential to be easily integrated into a chip-making facility. By 2010, the technology should be ready for manufacturing.
The first application of the technology will most likely be in a type of chip called field-programmable gate arrays (FPGAs), which have the flexibility to be programmed to complete a variety of tasks. FPGAs are typically used in the design stages of electronics and communication systems. However, once the bugs are worked out of the design, manufacturers replace FPGAs with faster, cheaper chips called application-specific integrated circuits (ASICs). Reducing the size and cost of FPGAs and increasing their speed has the potential to shift the balance between FPGAs and ASICs,