Smart cells will reconfigurable chips with faster speeds and low power usage.
A new class of computer chip is being developed. Huang’s reconfigurable computing device, called the smart cell, will combine the advantages of ASICs and FPGAs. It will incorporate more than a thousand individual processors wired onto a silicon substrate. Each processor will be responsible for performing a single operation, such as addition or multiplication, as data flows through the chip. Using a type of parallel computing called stream processing, the chip will complete hundreds of calculations simultaneously, enabling it to perform up to 300 times faster than microprocessors and about 15 times faster than FPGAs.
As with FPGAs, the smart cells will be programmed by software, enabling their functions to be updated continually as conditions change. But since the individual processors will be optimally design to perform specific functions, the chips will approach the power efficiency of ASICs. The architecture should scale easily, making it possible to build more powerful chips just by adding more processors.
To create the new architecture, Huang must find a way to integrate hundreds of individual processors in a single chip, something that has never been attempted before. An even more daunting task is developing a way to connect the processors to each other.