Onchip photonic communications for 2017 computer processors

Problems that need a lot of computing power and new architecture that will be needed to enable that speed. Click on the pictures for a larger image.

Communication challenge in ultradense computing devices. Chips are not full speed because communication is not fast enough.
DARPA MoleApps–Aim: 10**15devices/ cm**3
Currently: 17 nm half-pitch,3.5*10**11 /cm**2 demonstrated

Communication speed of 80 TB/s for full speed 2017 chips

Zettaflop workshop 2007

Computational challenge for systems biology and personalized medicine

Prospects for computing beyond CMOS

Programming techniques to harness Exaflops [and zettaflops]

Rethink hardware
–Parallelism is mainstream, but most cores are optimized for serial performance
–Need to design hardware for power and parallelism

Rethink software
– Massive parallelism
– Eliminate scaling bottlenecks replication, synchronization

Rethink algorithms
– Massive parallelism and locality
– Counting Flops is the wrong measure

Enabling technology for Zettaflops
Optical communication and nanomemory.

Zettaflop architecture report

Systems software for zettaflop systems
Things like billions of threads.

Energy of Computing in 2005

The biggest barrier to exaflops and zettaflops is the heat/power problem. Transistors may be cheap, but the energy they dissipate is not.
• Heat/power is not all in switching hardware; most of it is wattage for communication and memory. And clock switching is increasingly wasteful.
• In the long term, application programmers can help just as much as hardware engineers, by being less sloppy with memory use and precision demands.
We need to have new tools for analyzing power used in software. Less precision is more energy efficient (use just enough precision).