A Passive Microscale Solar Sail: Computer Chip Space Craft that Could Go Anywhere in the Solar System

Justin A. Atchison of Cornell University University proposes creating miniturized spacecraft with all systems made using computer chip technology and using only the active layer to achieve a weight of 7.5 milligrams or less. The system would act like a micro solar sail and could go like space dust anywhere in the solar system given enough time. The goal is self-contained “Microscale Infinite-Impulse” (MII) spacecraft capable of demonstrating significant, useful propellantless propulsion by virtue of its small length scale.

We consider spacecraft length scaling as a means of enabling achieving passive, feasible infinite-impulse orbits. Taking inspiration from the orbital dynamics of dust, this paper discusses the consequences of length scaling on acceleration due to solar radiation pressure and demonstrates its effectiveness on a candidate microscale spacecraft. We propose to fabricate this dime-sized spacecraft on a single ultra-thin substrate of silicon. This choice reduces the total mass to fewer than 7.5 mg and makes the spacecraft bus itself a solar sail, yielding a lightness number β of 0.0175. This architecture can provide passive solar sail formations and various passive methods of changing orbital energy. We also consider augmenting this architecture with traditional CP1 sail material (β of 0.1095) to reduce transfer times further. The paper surveys and compares passive methods of achieving a marginally stable sun-pointing attitude including the addition of fixed vanes and optical grating of the surface. The microscale infinite impulse (MII) spacecraft design replaces the traditional spacecraft subsystems with a single integrated circuit (IC). Our current fabrication efforts are directed at realizing this spacecraft as a simple sensing and transmitting circuit with standard IC tools.

The mass of such a 1 cm2 silicon substrate is 5.75 mg. For conservatism, the mass budget includes 30% margin, yielding a total mass of 7.46 mg, which is used in this paper’s calculations. The silicon fabrication process consists of additive and subtractive processes, which add or remove material from the substrate to form a device. The net contribution of these processes is assumed to be negligible.

A. Propulsion
Traditional propellant mechanisms such as chemical or ion thrust systems cannot be easily scaled to the IC level. A novel exception is so called “digital propulsion”. Lewis, et al. have successfully fabricated and demonstrated a device that delivers discrete amounts of thrust using microscopic chambers and chemical propellant. Though digital propulsion may prove relevant for our research in the long run, our current research is motivated primarily by propellantless propulsion, in hopes of enabling otherwise impossible missions and orbits. SRP, as described above, is among the potential propellantless-propulsion approaches.

B. Attitude Determination and Control
This paper has surveyed methods of achieving stable attitude orientations using passive SRP and spin stabilization. The sun-pointing architectures require a particular design and fabrication. Once released into an orbit, they behave passively. The momentum-stabilized architecture requires a method of spinning each chip about its major axis. A conceptually simple but perhaps costly solution is to design a mechanism to both spin and deploy each chip once in space. Alternatively, we are exploring outgassing as a means of producing torque. In this architecture, volatile material deposited on the edges of each chip would outgas in the vacuum of space to impart angular momentum, without the need for a spinning-deployment mechanism. Future research will also consider active control, perhaps with micro-electro-mechanical systems (MEMS) as proposed by McInnes.

C. Structure
The structure of the spacecraft consists of the volume of semiconductive substrate on which the other subsystems are fabricated. A gallium-arsenide substrate offers desirable radiation hardening and the opportunity to produce high efficiency solar cells. However, the cost of integrating MEMS subsystems on gallium arsenide may discourage its use. We therefore focus on a more common, silicon substrate. At 2300 kg/m3, solid Silicon is significantly denser than 100 kg/m3, the net density of a typical spacecraft. Nevertheless, the silicon substrate offers the most near-term opportunity to decrease total mass.

Like traditional structural subsystems, the substrate must support and mechanically interface the other subsystems, facilitate ground handling, and withstand vibrations during transportation and launch. The MII design is less concerned with vibration control because the natural frequencies of such a structure are be far higher than the likely attitude-control bandwidth of any launch vehicle and the MII itself . Instead, the design is based on the lightest structure on which components can be fabricated: the thinnest possible substrate for a required surface area.

For polished silicon wafers, this limit is approximately 200 μm. Thinner silicon is too brittle to machine. Siliconon-Insulator (SOI) wafers are an alternative. Such wafers consist of an ultra-thin layer of silicon on top of a siliconoxide layer. This substrate offers structural rigidity and handling during fabrication, after which the silicon-oxide layer can be removed to leave the processed device on the ultra-thin silicon layer. Then, arbitrarily thin silicon can be produced, although the thickness in this paper is restricted to no less than 25 μm for conservatism.

We estimate that sufficient functionality can be achieved in 1 cm2. In order to maximize use of the surface area, we consider flip-chip fabrication. In this process, two chips are manufactured such that their backsides can be mated and both chips face outward. This technique allows the MII spacecraft to incorporate devices whose fabrication techniques are incompatible by producing them separately and integrating them as a final step. Of primary interest is the placement of solar cells on both sides of the chip to ensure that power is always available, regardless of attitude.

The mass of such a 1 cm2 silicon substrate is 5.75 mg. For conservatism, the mass budget includes 30% margin, yielding a total mass of 7.46 mg, which is used in this paper’s calculations. The silicon fabrication process consists of additive and subtractive processes, which add or remove material from the substrate to form a device. The net contribution of these processes is assumed to be negligible.

D. Power
Solar cell power generation is both passive and based in semiconductor physics, making it a natural choice for power in this application. We focus on silicon-based, first-generation solar cells, which use a single-layer p-n junction diode to pass photovoltaic currents. With sets of individual cells strategically connected in parallel or series, an array can be designed with specific voltage and current characteristics to accommodate propulsive, attitude control, or payload requirements. Commercially available, high-efficiency cells commonly achieve specific power on the order of 200 W/kg. Integrated solar cells are much less efficient3. This inefficiency drives the design to devote the majority of the available silicon surface to photovoltaics. Likewise, electrochemical batteries are difficult to integrate. It may be that an MII spacecraft will simply be powerless in eclipse. Alternatively, thin film capacitors printed on the chip might be used to store power. Solar cells produce electric power proportional to the cosine of the pitch angle. For this reason, sun-pointing attitude solutions offer an important advantage over other attitudes.

E. Communications
Following Sputnik’s example and facing the challenges of little available power, we conceive the communications subsystem as a transmit-only beacon. The data consists of a single beep at a single frequency—a binary output based on the presence or absence of the carrier. There is no signal per se carried on that frequency.

For this simple transmission to be tracked from a ground station, it must be powerful enough to overcome free-space loss, atmospheric attenuation, and other noise sources. The communication link’s carrier-to-noise-ratio C/N is therefore a useful measure of goodness. This ratio is influenced by the signal’s frequency, the orbit’s altitude, the transmitter’s losses and power, atmospheric conditions, and antenna efficiency. A single chip can accomplish only so much. A simple way to close the link budget is to select a ground station with high enough gain. For example, a candidate ground segment might use one of the Deep Space Exploration Society’s two 60 foot diameter parabolic dishes located in a radio-quiet region of Colorado. With an antenna gain of 32 dB, this dish represents an extremely sensitive publicly accessible receiver. Roughly speaking, a C/N of 10 at 8 GHz requires only 5 mW of emitted power to reach ground from LEO.

A simple RC-tank charging circuit can produce periodic bursts of power. In the baseline architecture, solar power charges a capacitor until a critical voltage is reached and a transistor is opened, releasing the stored energy. This energy is sent through an LC oscillator and is emitted as RF energy via two antennas. This sequence results in a pulsed oscillating signal. When sunward, the spacecraft exhibits an 8 s charging constant. The performance of RLC circuits depends on temperature, implying that the pulse frequency will vary with temperature. This dependence can be modeled or characterized experimentally and used to infer temperature from the beacon’s center frequency

Current Status
They are developing a simple hardware demonstration of the MII bus in the Cornell NanoScale Science & Technology Facility (CNF). Their most recent efforts have focused on the RLC oscillator. Having achieved our target 10 nF/cm2 capacitance density using silicon-dioxide as a dielectric layer, they are fabricating a series of inductors based on a three-layer octagonal design by Craninckx. Below is a photograph of their current oscillator at 20x magnification. Concurrently, members of their group are exploring the challenges associated with solar cell integration and have begun fabrication on organic solar cells which are compatible with many other fabrication processes. Once the chip is fabricated, they will begin thermal vacuum chamber and sun simulator testing.

You can bond the electronics to straight solar sail material for better/different performance and missions.

There are a lot of other technology developments that could be leveraged into this kind of system.

The MEMS 3D origami where MEMS are folded into 3 dimensional structures. Chips made with graphene or carbon nanotubes. Recently 5 Ghz electronics were printed using carbon nanotube ink.

If these spacecraft chips could be created in cheap mass quantities then it would be a technology pathway to creating a Dyson shell of solar power gathering devices. Being able to make a lot of chip spacecraft would have many interesting possibilities in terms of massive arrays, sensors all over the solar system etc…