Graphene holds the promise of 10-times faster speed than silicon chips, plus the ability to be integrated with exiting semiconductor fabrication techniques. It was thought that 2017 sub-10 nanometer lithography would be needed to bring Graphene into the semiconductor computer roadmap. Professor Feng Wang at UC Berkeley claims to have demonstrated a technology that can electrically tune graphene’s bandgap, enabling it to be used for digital transistors long before lithography hits sub-10 nanometer sizes.
The researchers speculated that a new kind of graphene gate array would be possible using the technique to dynamically reconfigure millions of gates, each with both top and bottom electrodes, by retuning their bandgaps on-the-fly.
“All you need is dual gates at all positions, then you could change any location to be either a metal or a semiconductor electrically,” said Wang.
Wang, along with his post-doctoral fellow Yuanbo Zhang, his graduate student Tsung-Ta Tang and their UC Berkeley and Lawrence Berkeley National Laboratory colleagues, are next planning to demonstrate working circuits using the technique. The group is particularly interested in demonstrating optical emissions as high-energy electrons shed photons to jump the band-gap.
Wang used exfoliation to fabricate two parallel graphene monolayers atop each other, then attached gate electrodes to the top and bottom of the bilayers. Electrical connections for the source and drain were made along the edges of the bilayer sheets. By varying the gating voltages on the top and bottom gates independently, the team was able to demonstrate an electrically tunable bandgap that varied between zero (a metal) and 250 milli-electron volts (a semiconductor). That was only a fraction of the size of bandgaps in current semiconductors (germanium and silicon have bandgaps of 740- and 1,200-meV, respectively) but wide enough to fabricate digital circuitry