Lithographic Graphitic Memories

HPC Wire reports that advances by the Rice University lab of James Tour have brought graphite’s potential as a mass data storage medium a step closer to reality and created the potential for reprogrammable gate arrays that could bring about a revolution in integrated circuit logic design. (H/T Sander Olson)

In a paper published in the online journal ACS Nano, Tour and postdoctoral associate Alexander Sinitskii show how they’ve used industry-standard lithographic techniques to deposit 10-nanometer stripes of amorphous graphite, the carbon-based, semiconducting material commonly found in pencils, onto silicon. This facilitates the creation of potentially very dense, very stable nonvolatile memory for all kinds of digital devices.

With backing from a major manufacturer of memory chips, Tour and his team have pushed the technology forward in several ways since a paper that appeared last November first described two-terminal graphitic memory. While noting advances in other molecular computing techniques that involve nanotubes or quantum dots, he said none of those have yet proved practical in terms of fabrication.

Not so with this simple-to-deposit graphite. “We’re using chemical vapor deposition and lithography — techniques the industry understands,” said Tour, Rice’s Chao Professor of Chemistry and a professor of mechanical engineering and materials science and of computer science. “That makes this a good alternative to our previous carbon-coated nanocable devices, which perform well but are very difficult to manufacture.”

James Tour of Rice university has developed easily accessible memory devices based upon stripes of chemical vapor deposited (CVD) nanosized irregular discs of graphitic material that can be layered in stripes ≤10 nm thick with controllable lengths and widths. These lithographic graphitic stripes, which can be easily fabricated in large quantities in parallel by conventional fabrication techniques (such as CVD and photo- or e-beam lithography), with yields >95%, are shown to exhibit voltage-induced switching behavior, which can be used for two-terminal memories. These memories are stable, rewritable, and nonvolatile with ON/OFF ratios up to 10^7, switching times down to 1 μs (tested limit), and switching voltages down to 3−4 V. The major functional parameters of these lithographic memories are shown to be scalable with the devices’ dimensions.

Graphite’s other advantages were detailed in Tour’s earlier work: the ability to operate with as little as three volts, an astoundingly high on/off ratio (the amount of juice a circuit holds when it’s on, as opposed to off) and the need for only two terminals instead of three, which eliminates a lot of circuitry. It’s also impervious to a wide temperature range and radiation; this makes it suitable for deployment in space and for military uses where exposure to temperature extremes and radiation is a concern.

Tour’s graphite-forming technique is well-suited for other applications in the semiconductor industry. One result of the previous paper is a partnership between the Tour group and NuPGA (for “new programmable gate arrays”), a California company formed around the research to create a new breed of reprogrammable gate arrays that could make the design of all kinds of computer chips easier and cheaper.

Currently, antifuse FPGAs can be programmed once. But this graphite approach could allow for the creation of FPGAs that can be reprogrammed at will. Or-Bach said graphite-based FPGAs would start out as blanks, with the graphite elements split. Programmers could “heal” the antifuses at will by applying a voltage, and split them with an even higher voltage.

Such a device would be mighty handy to computer-chip designers, who now spend many millions to create the photolithography mask sets used in chip fabrication. If the design fails, it’s back to square one.

Carbon-based memory architectures promise to revolutionize FPGA design, according to the founder of a chip startup.

Startup NuPGA was founded by Zvi Or-Bach, a winner of the EE Times Innovator of the Year Award. He previously founded eASIC and Chip Express. Or-Bach has applied for a patent, along with Rice University, for its carbon-based memory process developed by professor James Tour. The approach uses graphite as the reprogrammable memory element inside vias on otherwise conventional FPGAs.

“Using graphite in the vias as fuse is a very interesting concept,” said Dean Freeman, senior analyst at Gartner Inc. “We are going to see a lot of very innovative, creative thinking along these lines in the next five years.”

Rice University researchers developed a bulk chemical process that converted nanotubes into nanoribbons, providing the raw material needed to perfect a technique based on using voltage pulses to make or break connections–essentially turning the carbon ribbons into reprogrammable switches. NuPGA plans to harness these reprogrammable switches in FPGAs by inserting graphite into vias between chip layers, allowing them to be reconfigured on-the-fly.

“Graphene can become interesting when it is shaved down to below 10-nanometer widths into ribbon structures, making it much easier to modulate at low voltages,” said Tour. “Graphene won’t be ready to go head-to-head with Intel until 2015, when lithography dips below that 10-nanometer size. By that time, much of the market could already be using thin films of carbon materials for bulk electronics in places where silicon can’t be used today.”

By making thin films from his slurries of carbon nanotubes–what he calls “graphene nanoribbons”–Tour perfected the memory architecture to be used in reprogrammable switches in NuPGA’s chips. The process allows a voltage pulse to reprogram FPGAs by making or breaking the connection pathway through graphite-filled vias.