Days 2 and 3 of the International Electron Devices Meeting blogged By Sander Olson

This is a follow up of Sanders report of day one of the International Electron Devices Meeting Sander Olson reports on Day 2 and 3.

Days 2 and 3 of the International Electron Devices Meeting focused on both conventional and radical switching paradigms to continue Moore’s law as long as possible. Conventional techniques, such as strained silicon and metal gates, will form the basis for the next several technology nodes for reducing leakage and maximizing performance of silicon transistors. Intel engineers described the technology for their upcoming 32 nm technology node, which features 2nd generation high-K and metal gates, and 4th generation strained silicon. However, such techniques will not by themselves be sufficient for more than a few process generations, and so other more radical techniques will be needed. As integrated circuits transistor budgets grow, multi-billion dollar ICs will become increasingly common. Designing such multi-billion transistor chips is causing difficulties within the industry. Carl Anderson of IBM reported that router complexities, wiring variability, power density, and electrical migration issues are all making IC design more difficult than ever. Moreover, there are limits to the number of chip designers that even a large company like Intel or IBM can hire. In 1990 IBM’s chip designers were expected to design 50 circuits per year per designer. IBM currently employs thousands of chip designers – many more than 20 years ago – but each designer is now expected to design up to 5 million circuits per year. This massive increase is due to extensive use of increasingly sophisticated design and layout software, such as Simulation Program with Integrated Circuit Emphasis (SPICE). IBM is close to the limit of the number of chip designers that it can hire, and is therefore continuing to leverage increasingly sophisticated design tools in an effort to keep up with burgeoning transistor budgets.

Maintaining high levels of reliability is also becoming problematic with modern IC designs. Intel’s S. Borkar noted that chip design complexity is increasing exponentially, and creating dependable chips is becoming progressively harder. Intel sees the need to find ways to design reliable chips with unreliable components. In particular, chip designers are simply unable to prevent variability from cropping into the latest chips, which is making it exceedingly difficult to ensure reliable operation and uniform performance. K. Michaels of PDF solutions noted that 32 nm chip designs require chip designers to model 1500 different types of unique transistors. Michaels argued that “Logic Templates” were a potential solution to this problem.

One concept which is attracting increasing attention is 3-d chip technology, which garnered substantial discussion at the conference. Silicon scaling will probably end at either the 22 nm or 15 nm nodes, and after that the industry will need to transition to some form of 3d technology to compensate. 3-d methods include through-silicon-vias and 3-d die-to-wafer integration. In order to make this work engineers need to find ways to thin wafers to as little as 10 microns, mostly by chemical polishing. But 300 mm wafers have successfully been thinned to 7 microns, and no electrical degradation was found on these thinned wafers.

Many papers were given on multi-gate, high-electron mobility, spintronics, and carbon transistors. Multi-gate transistors generally consist of a raised gate surrounding the transistor channel, and have the potential to reduce off-state leakage. Chip designers were originally hoping to insert multi-gate devices at the 32nm node, but due to manufacturing and other technical difficulties won’t insert multi-gate transistors into mainstream ICs until the 12 nm node, if that node is ever reached. The first Indium Gallium Arsenide FinFETs have been fabricated and are exceptionally fast but these transistors are expensive to fabricate. “Spintronics” takes advantage of the “spin” of an electron rather than an electron’s charge. Spintronics devices could potentially dissipate a fraction of the power that charge-based devices consume. The first spin-based MOSFET transistors have been fabricated,

The most promising transistor, technology, however, appears to come from carbon transistors. The IEDM labeled graphene transistors as one of the research materials of greatest importance. Graphene is a single sheet of carbon with unrivaled mechanical, electronic, and thermal properties. The number of papers on graphene has expanded exponentially, and IBM has demonstrated a graphene Field Effect Transistor (FET) operating at 50 Ghz. Moreover, IBM is confident that 100 GHz transistors should soon be feasible. Furthermore, graphene can be used to make either conventional charge-based devices, or alternately can be used to make spintronic devices. One speaker at the conference revealed that “spin” has been demonstrated in both single and multiple layers of graphene. Researchers have made lithographically patterned 1-2 nanometer “nanoribbons” of graphene with high-mobility, high on-off ratios, and high critical current density. The prospects for graphene are hampered by the fact that graphene currently has a zero energy gap, so designers need to engineer a sufficient gap in order for it to be suitable for digital electronics. There are also issues with rough edges on the ribbons as well as controlled-growth difficulties. But none of these issues are considered showstoppers, and graphene could end up being used in commercial semiconductors as early as 2020