Taiwan Semiconductor Manufacturing Will Skip 22 nanometer node and go Directly to 20 nanometer in 2013

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EEtimes reports, at the Taiwan Semiconductor Manufacturing’s technology conference, the world’s largest silicon foundry provided details about its 20-nm strategy and its 20-nm CMOS process, which will be the company’s main technology platform after the 28-nm node. TSMC will also not offer an 18-nm process

* the move to 20-nm creates a better gate density and chip performance to cost ratio than a 22-nm process technology
* TSMC is currently shipping its 40-nm process. Then, it will move to the 28-nm node.
* TSMC’s high-performance 20-nm process is slated to move into risk production in the third quarter of 2012, with volume production scheduled for the first quarter of 2013. Two quarters after the high-performance technology, TSMC is slated to roll out its low-power process.

TSMC’s 20-nm process is a 10-level metal technology based on a planar technology. It will feature a high-k/metal gate scheme, strained silicon and newfangled ”low-resistance” copper ultra-low-k interconnects–or what it calls ”low-r.” For the 20-nm node, it will only offer a high-k/metal-gate scheme for the gate stack–and not a silicon dioxide option.

TSMC (Hsinchu) will continue to use 193-nm immersion lithography at 20-nm, but it will also deploy a double-patterning scheme. Unlike its previous processes in recent times–which focused on low power first–TSMC’s initial 20-nm process will be a high-performance technology. Following that process, it will roll out a low-power technology.

With the announcement, TSMC is seeking to gain an edge over its leading-edge rivals, such a GlobalFoundries, Samsung and UMC. Both Samsung and UMC have said little or nothing about their respective 2x-nm nodes.

By going to 20-nm, TSMC is leapfrogging one rival–at least on paper. Recently, GlobalFoundries Inc. said it is starting work on its 22-nm CMOS process, which is due out in the second half of 2012

TSMC’s 20-nm process features 10-level metal layers, although customers may typically use 6-to-8 layers, he said. The company continues to push bulk CMOS silicon at 20-nm, as it will not migrate to silicon-on-insulator (SOI) or other transistor structures such as FinFETs.

Chiang believes that 20-nm could be the last node that TSMC uses a planar structure. Following that node, possibly 14-nm, TSMC may be forced to go to a FinFET or a 3-D structure.

TSMC is also evaluating other lithography candidates, namely EUV and maskless. The foundry provider will initially go with 193-nm immersion at 20-nm production, but it may also deploy EUV or maskless, depending on the viability of those technologies

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