The company said it has achieved 1-mA per micron on-current, the world’s highest level for a nanowire transistor, by reducing parasitic resistance and improving the on-current level by 75 percent.
The silicon nanowire transistor can suppress off-leakage and achieve further short-channel operation, because its thin wire-shaped silicon channel (nanowire channel) is effectively controlled by the surrounding gate. However, parasitic resistance in the nanowire-shaped source/drain, especially in the region under the gate sidewall, degrades the on-current. Toshiba claims to have overcome this problem by optimizing gate fabrication and significantly reducing the thickness of the gate sidewall, from 30-nm to 10-nm. Low parasitic resistance was realized by epitaxial silicon growth on the source/drain with a thin gate sidewall, which leads to a 40 percent increase in on-current. The company also achieved a further 25 percent increase in current performance by changing the direction of the silicon nanowire channel
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