Mentor Produces 16-nanometer Test Chips but there are Big Uncertainties

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Joseph Sawicki, vice president and general manager of the Mentor Graphics Corp.’s Design to Silicon Division, has said that the first 16-nm test chips go out a couple of months ago.

The current 16nm work is mostly intellectual-property development.

Sawicki cited some big bets that foundries and design teams are being forced to put on the table. One is the choice of gate-first or gate-last processing for high-k/metal-gate gate stacks. “It seems clear that gate-first will provide greater density,” Sawicki said, but he warned that other uncertainties remain, such as potential differences in process variations and even whether both approaches will scale below 20-nm.

The questions are critical to chip designers because the two major foundry powers—Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and Globalfoundries Inc.—have taken opposite approaches, leading them to have quite different design rules. Since there will not be easy portability between the two foundry groups, design teams may have to pick one track or the other.

There is also the still-unresolved lithography roadmap. Printers for critical layers at 16-nm might be EUV systems, or they might be massively-parallel e-beam direct-write systems. Or we might still be using 193-nm immersion lithography. Each choice requires different treatment of design data before the masks are made, and each would have different design rules.

“Despite all its problems, our bet is that we will still be using immersion at 193-nm,” Sawicki said. “It will require us to use pixilated light sources and pixilated masks, with co-optimization between the source pattern, the mask shapes, and the design rules. And that will mean we will require about 20 teraFLOPS of computing power to prepare one mask layer in a reasonable time.”

Another option is going to full 3D chip stacks. We may have to model the TSVs themselves as active devices instead of treating them like giant vias.

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