The San Diego Supercomputer Center (SDSC) at the University of California, San Diego, will provide expertise to a multi-year technology investment program to develop the next generation of extreme scale supercomputers.
The first two phases of the [exaflop scale] project extend into 2014, and a full system design and simulation is expected at the completion of those phases in 2014. Phases 3 and 4 of the project, which have not yet been awarded, are expected to result in a full prototype system sometime in 2018
DARPA funded four groups — led by NVIDIA Corp., Intel Corp., the Massachusetts Institute of Technology and Sandia National Laboratories — to develop UHPC prototypes. A fifth group, led by the Georgia Tech Research Institute (GTRI), will develop applications, benchmarking and metrics that will be used to drive UHPC system design considerations and support performance analysis of the developing system designs.
The new DARPA Ubiquitous High Performance Computing (UHPC) initiative is a $100 million challenge, which will require development of revolutionary approaches not bound by existing computing paradigms.
During the first phases of the award, SDSC’s Performance Modeling and Characterization (PMaC) laboratory will assist the Intel-DARPA project by analyzing and mapping strategic applications to run efficiently on Intel hardware. Applications of interest include rapid processing of real-time sensor data, establishing complex connectivity relationships within graphs (think of determining “six degrees of Kevin Bacon” relationships on Facebook), and complex strategy planning
According to Intel, the project will focus on new circuit topologies, new chip and system architectures, and new programming techniques to reduce the amount of energy required per computation by two to three orders of magnitude. That means such extreme scale systems will have to require 100 to 1,000 times less energy per computation than what today’s most efficient computing systems consume.
“We are working to build an integrated hardware/software stack that can manage data movement with extreme efficiency,” said Allan Snavely, associate director of SDSC and head of the supercomputer center’s PMaC lab. “The Intel team includes leading experts in low-power device design, optimizing compilers, expressive program languages, and high-performance applications, which is PMaC’s special expertise.”
SDSC plans to build the high-performance computing community’s first flash memory-based supercomputer system named Gordon, to enter operation in 2011
When fully configured and deployed, Gordon will feature more than 200 teraflops of total compute power (one teraflop or TF equals a trillion calculations per second), 64 terabytes (TB) of DRAM (digital random access memory), 256 TB of flash memory, and four petabytes of disk storage (one petabyte or PB equals one quadrillion bytes of data). For sheer power, when complete, Gordon should rate among the top 30 or so supercomputers in the world.
A key feature of Gordon will be 32 “supernodes” based on an Intel system utilizing the newest processors available in 2011, and combining several state-of-the-art technological innovations through novel virtual shared-memory software provided by Scale MP, Inc. Each supernode consists of 32 compute nodes, capable of greater than 195 gigaflops/node (one gigaflop or GF equals a billion calculations per second) and 64 gigabytes (GB) of DRAM. A supernode also incorporates 2 I/O nodes, each with 4 TB of flash memory. When tied together by virtual shared memory, each of the system’s 32 supernodes has the potential of more than 6 TF of compute power and 10 TB of memory (2 TB of DRAM and 8 TB of flash memory).
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