IBM’s all silicon optical transceivers house modulators, wave guides, wavelength-division multiplexers, switches and detectors all cast the same CMOS die.
* IBM (Armonk, N.Y.) heralded silicon nanophotonics as the enabler for future exascale processors
* IBMs CMOS silicon nanophotonics technology can meet the requirements for exascale systems, by scaling up per-chip transceiver bandwidth and integration density
* CISN technology is currently being licensed to partners, and will begin to appear in commercial transceivers starting in 2011.
One major stumbling block recently removed by IBM for its CISN technology was the ability to bury a germanium layer at the bottom of its CMOS stack. Others like Freescale, working with startup Luxtera, have demonstrated silicon optical transceivers using that use a germanium-last process, but IBM claims its germanium-first process enables a 10-to-1 reduction in die size, enabling 65-nanometer CMOS chips to house silicon optical transceivers in just a half a square millimeter (which can be ganged together for terabit-per-second speeds in less than five-by-five millimeters).
IBM is currently characterizing the manufacturability of its CISN process in commercial foundries, and predicts that the first availability of CMOS optical transceivers from its licensees will begin next year. IBM predicts that its CISN will then work its way from connecting systems to connecting boards in the same system, to connecting chips on the same board, to eventually connecting cores on the same CMOS microprocessor by 2016.
In addition to combining electrical and optical devices on a single chip, the new IBM technology can be produced on the front-end of a standard CMOS manufacturing line and requires no new or special tooling. With this approach, silicon transistors can share the same silicon layer with silicon nanophotonics devices. To make this approach possible, IBM researchers have developed a suite of integrated ultra-compact active and passive silicon nanophotonics devices that are all scaled down to the diffraction limit – the smallest size that dielectric optics can afford.
“Our CMOS Integrated Nanophotonics breakthrough promises unprecedented increases in silicon chip function and performance via ubiquitous low-power optical communications between racks, modules, chips or even within a single chip itself,” said Dr. Yurii A. Vlasov, Manager of the Silicon Nanophotonics Department at IBM Research. “The next step in this advancement is to establishing manufacturability of this process in a commercial foundry using IBM deeply scaled CMOS processes.”
By adding just a few more processing modules to a standard CMOS fabrication flow, the technology enables a variety of silicon nanophotonics components, such as: modulators, germanium photodetectors and ultra-compact wavelength-division multiplexers to be integrated with high-performance analog and digital CMOS circuitry. As a result, single-chip optical communications transceivers can now be manufactured in a standard CMOS foundry, rather than assembled from multiple parts made with expensive compound semiconductor technology.
The density of optical and electrical integration demonstrated by IBM’s new technology is unprecedented – a single transceiver channel with all accompanying optical and electrical circuitry occupies only 0.5mm(2) – 10 times smaller than previously announced by others. The technology is amenable for building single-chip transceivers with area as small as 4x4mm(2) that can receive and transmit over Terabits per second that is over a trillion bits per second.
Artist’ concept of a future 3D silicon processor chip with optical IO layer featuring on-chip nanophotonic network
Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
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