Beyond flash memory

New Electronics (UK) looks at technologies that may succeed flash memory.

Every memory technology other than dram or flash has looked promising right up to the point where it has hit the market – and then been outrun by devices with a much longer heritage that may not be as convenient to use, but which can deliver the highest number of bits at the lowest cost. The last non volatile technology to have made it big is flash, which evolved from earlier work on ultraviolet erasable (eprom) and electrically erasable read only memories (eeproms)

Phase change memory

There is concern growing over the ability of flash to continue scaling much past the 22nm generation, a technology such as phase change has the advantage of being much easier to use: it behaves much more like an sram in terms of reads and writes. Phase change memory does not need the complex erase and programming sequences that flash does, although on chip circuitry has to generate the right set and reset pulses.

The only phase change memory found in a mass-market design so far is a 512Mbit drop in replacement for NOR flash that has shipped in a small number of Samsung GSM phones, according to teardowns by Chipworks and TechInsights. The NOR flash layout does not have a 3d counterpart being developed, so is more vulnerable to competition from new memory technologies.

Some of the lifetime issues with phase change may be solved by work conducted by IBM’s Almaden laboratories. The researchers there have analysed how the elements within the phase change alloy move around under stress. For example, tellurium – used in one of the main alloys – will tend to move away from the main current path. However, the team found that a type of current pulse that is normally bad for these memories will partially reverse this process and extend the lifetime of a memory cell.


Many are enthusiastic over the prospects for another heat triggered memory: metal oxide resistive ram (ReRAM). He is not alone: researchers around the world have seized on ReRAM as a potentially better bet than phase change or flash memory.

A big attraction is material simplicity. Resistance switching was first found in materials such as lead zirconium titanate (PZT) – a material that has been used in ferroelectric memories, another one time contender for low cost non volatile storage. Unfortunately, PZT is hard to combine with cmos processes – the main reason why ferroelectric memories are today restricted to low density, specialised applications, such as data storage for energy meters.

Once device researchers observed similar resistive switching in binary oxides such as tantalum pentoxide – which has been used in dram capacitors – they became much more enthusiastic about the prospects for ReRAM. Things seemed to get better with the realisation that ReRAMs could be formed into 3d stacks.

Seemingly more manufacturable, ReRAM is facing plenty of problems. One is that nobody is entirely sure how it works.

Similar to phase change memories, the high temperatures that the filaments reach could prove a problem for the long term reliability of ReRAMs. Better understanding of what causes reaction in ReRAMs may make it possible to reset a cell to its oxidised, high resistance, state without resorting to high temperatures induced by current.


In 2005, Grandis and Sony discovered that a slightly different mechanism based on spin polarisation could be used to control the magnetic orientation of layers in an MRAM cell. The spin-torque transfer MRAM was born and it kickstarted development of a new generation of devices that may prove to be the answer for the long awaited unified memory.

The spin torque transfer MRAM faces big problems. The materials degrade at the temperatures needed to lay down the dielectric and metal layers used for on chip interconnect, making the memory hard to integrate on SoCs. The relative size of the memory cell will limit its use in standalone memories and, if other 3d techniques take over, threaten its use on chip.

How 3d stacking will affect memory will depend on relative cost.

Antun Domic, general manager of the implementation group at Synopsys, reckons the incremental cost of stacking as the technique moves into volume will be around $150 per wafer – or around 5% of the cost of a single fully processed wafer. Some, such as Jan Vardaman, president of Techsearch, think this could be an underestimate. However, if 3d is to be used in volume, its incremental cost will need to be a lot less than 10% per stacked wafer.

If manufacturing costs come down – and memory stacking for mobile phones has demonstrated how cheaply it can be done – it will give memory makers another degree of freedom. It may be cheaper to stick with flash and simply use more chips than to bear the cost of moving to completely new memory technologies that, because of thermal problems during manufacture or low yields, never quite become clear winners.

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