Researchers at Harvard and MITRE produce world’s first programmable nanoprocessor with potential for 2 Terahertz switching

False-colour scanning electron microscopy image of a programmable nanowire nanoprocessor super-imposed on a schematic nanoprocessor circuit architecture. Photo courtesy of Charles M. Lieber.

Engineers and scientists collaborating at Harvard University and the MITRE Corporation have developed and demonstrated the world’s first programmable nanoprocessor. Nanowire tiles can perform arithmetic and logical functions and are fully scalable. In a significant step forward in complexity and capability for bottom-up assembly of nanoelectronic circuits, Yan et al. demonstrate scalable and programmable logic tiles based on semiconductor nanowire transistor arrays. The same logic tile, consisting of 496 configurable transistor nodes in an area of about 960 square micrometres, can be programmed and operated as a full-adder or full-subtractor circuit, and used for various other functions including multiplexers. It should be possible in future to cascade these logic tiles to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Journal Nature – Programmable nanowire circuits for nanoprocessors

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ~960 μm2. The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input–output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

The versatile, nanoscale circuits are assembled into tiny tile-like nanoprocessors from sets of precisely engineered and fabricated germanium-silicon wires with functional oxide shells, having a total diameter of only 30 nanometers. Shown here are atomic force (left) and optical microscopy (center) images of a programmable nanowire nanoprocessor, and a corresponding schematic (right) of the nanowire circuit architecture. Image courtesy of Charles M. Lieber.

The groundbreaking prototype computer system, described in a paper appearing today in the journal Nature, represents a significant step forward in the complexity of computer circuits that can be assembled from synthesized nanometer-scale components.

It also represents an advance because these ultra-tiny nanocircuits can be programmed electronically to perform a number of basic arithmetic and logical functions.

“This work represents a quantum jump forward in the complexity and function of circuits built from the bottom up, and thus demonstrates that this bottom-up paradigm, which is distinct from the way commercial circuits are built today, can yield nanoprocessors and other integrated systems of the future,” says principal investigator Charles M. Lieber, who holds a joint appointment at Harvard’s Department of Chemistry and Chemical Biology and School of Engineering and Applied Sciences.

The work was enabled by advances in the design and synthesis of nanowire building blocks. These nanowire components now demonstrate the reproducibility needed to build functional electronic circuits, and also do so at a size and material complexity difficult to achieve by traditional top-down approaches.

Moreover, the tiled architecture is fully scalable, allowing the assembly of much larger and ever more functional nanoprocessors.

“For the past 10 to 15 years, researchers working with nanowires, carbon nanotubes, and other nanostructures have struggled to build all but the most basic circuits, in large part due to variations in properties of individual nanostructures,” says Lieber, the Mark Hyman Professor of Chemistry. “We have shown that this limitation can now be overcome and are excited about prospects of exploiting the bottom-up paradigm of biology in building future electronics.”

An additional feature of the advance is that the circuits in the nanoprocessor operate using very little power, even allowing for their miniscule size, because their component nanowires contain transistor switches that are “nonvolatile.”

This means that unlike transistors in conventional microcomputer circuits, once the nanowire transistors are programmed, they do not require any additional expenditure of electrical power for maintaining memory.

“Because of their very small size and very low power requirements, these new nanoprocessor circuits are building blocks that can control and enable an entirely new class of much smaller, lighter weight electronic sensors and consumer electronics,” says co-author Shamik Das, the lead engineer in MITRE’s Nanosystems Group.

“This new nanoprocessor represents a major milestone toward realizing the vision of a nanocomputer that was first articulated more than 50 years ago by physicist Richard Feynman,” says James Ellenbogen, a chief scientist at MITRE.

The research team at MITRE comprised Das, Ellenbogen, and nanotechnology laboratory director Jim Klemic

10 pages of supplemental material

Ge/Si core/shell nanowire synthesis.

Ge/Si nanowires were synthesized using the Aunanocluster- catalyzed methodology described previously. 10 nm diameter gold nanoparticles (Ted Pella) were dispersed on the oxide surface of silicon/SiO2 substrate (600 nm oxide) and placed in the central region of a quartz tube reactor system. The Ge-core is synthesized at 270 oC and 450 torr, with 30 sccm germane (GeH4, 10% in H2) and 200 sccm H2 as the Ge reactant and carrier gas, respectively. The growth was carried out for 40 min to yield NWs with >35 μm length. Without opening the growth system, the epitaxial Si shell was then grown at 460 oC and 5 torr for 2 min, using 5 sccm pure silane (SiH4) as the Si source. The growth system was pumped down to 3 mtorr and purged with H2 for 5 min between the growth of Ge-core and Si-shell.

ALD growth of oxide dielectric shells.

The device substrate with Ge/Si NWs and source/drain contacts was placed in the ALD chamber (Savannah-100, Cambridge NanoTech) heated to 200 oC. Trimethyl aluminum [Al(CH3)3, TMA], tetrakis(dimethylamino)zirconium {Zr[N(CH3)2]4} and water were used as precursors. Each Al2O3 deposition cycle consisted of 0.015 s water vapor pulse, 8 s N2 purge, 0.015 s TMA pulse and 8 s N2 purge. Each ZrO2 deposition cycle consisted of 0.015 s water vapor pulse, 10 s N2 purge, 0.25 s Zr-precursor pulse and 15 s N2 purge. To form the charge-trapping dielectric structure shown in Fig. 1b, a deposition sequence of 25 cycles Al2O3, 55 cycles ZrO2 and 55 cycles Al2O3 was used.

Contact Printing of NWs (nanowires).

Ge/Si NWs were transferred from growth substrates to device substrates by a shear printing process where shear force determines the density and alignment of NWs. First, oxygen plasma treated (80 W, 1 min) device substrates (600 nm SiO2/Si) were patterned by photolithography (Shipley S1805 diluted 50 % in Thinner-P, MicroChem) to define a region where NWs will be deposited. The dimension of the region was typically ~1 cm (width) by ~1 mm (length). Second, the patterned device substrate was mounted onto a fixed stage whose movement can be controlled by a micromanipulator. Approximately 50 μL of mineral oil (heavy mineral oil, Sigma-Aldrich) was drop-casted onto the device substrate to serve as a lubricant. Third, the NW growth substrate (~1 cm by 2 cm) was brought into contact with the device substrate (NWs facing the device substrate) and a pressure of ~3.43 N/cm2 was applied while the device substrate was slid with a constant velocity of ~5 mm/min. These procedures produced an average printing density of ~1 Ge/Si NW per micron.

Fabrication of nanowire logic tile.
The large-area Ge/Si NW array was first patterned into proper dimensions for device fabrication, using an inductively coupled plasma reactive ion etching (ICP-RIE, Surface Technology Systems). SF6 was used as etchant and electron beam lithography (EBL, with PMMA 950-C2, Microchem) was used to mask regions for devices. Dark-field optical microscopy was used to register the positions of individual NWs, and then source/drain contacts were defined by EBL followed by wet etching in 1:7 buffered oxide etchant (BOE, Transene) for 5 seconds and thermal evaporation of 70 nm Ni. The dielectric layers were deposited by ALD followed by EBL and metallization to define top-gate metal lines (Cr/Au, 2/70 nm respectively). The dielectric over the outer metal was etched with 1:7 BOE for 15 s to allow electrical access to the devices. Finally, EBL and metal evaporation were used to connect source/drain/gate electrodes to the outer metal pads.

Comparison of nanowire logic tile and top-down CMOS logic

First, the effective area per transistor without overhead in the un-optimized NW array demonstrated in this work is ~1.9 micrometers^2, which is larger than that of 0.09 micrometers^2 in the logic gates ofa the present 32-nm CMOS generation9. The projected area per NW transistor may be reduced by up to several orders of magnitude in the future using dense packed NWs, which have been demonstrated by Langmuir-Blodgett assembly, and based on the reported scaling of chargetrapping devices. Second, the estimated power consumption of each NW logic gate is ~0.9 microWatts based on VDD of ~3 V and on-state current of ~0.3 microamps. This is larger than the 10-100 nW per gate consumed in 32-nm CMOS. However, the use of complementary p-type/n-type NW devices would eliminate static power dissipation and could reduce substantially power consumption per NW logic gate. Third, the prototype demonstrated in this work was developed to demonstrate correct static operation and was not optimized for maximum operating speed. Simulations carried using both measured NW properties and projected improved circuit designs suggest that a circuit speed on the order of 100 MHz would be achievable, which is comparable to clock speeds required in real-time, low-power microcontrollers but less than the 5 GHz achievable in conventional CMOS for high-performance computing. It is noteworthy that the speed of the nanoprocessor is not limited by the intrinsic characteristics of NWs, as previous studies of Ge/Si NWFETs with 40 nm channel length has shown potential for 2 THz switching, which defines an upper limit for Ge/Si NWFET-based logic operations.

Schematic of key components of the two-block PNNTA tile, including assembled and patterned Ge/Si nanowires (cyan) with source and drain electrodes (blue), and charge-trapping trilayer gate dielectric (purple) and metal gate lines (grey)

Closer but still 1000 times too big for the adder part of the Feynmann Grand Prize

Design and Construct a Functional Nano-scale Computing Device

The prize winner must also design, construct and demonstrate the performance of a digital computing device that fits into a cube no larger than 50 nanometers in any dimension. The computing device must be capable of:

* adding accurately any pair of 8-bit binary numbers, discarding overflow.
* accepting input signals of specified types (see below).
* producing its output as a pattern of raised nanometer-scale bumps on an atomically precise and level surface.

Here is a paper that discusses different ways to implement adders

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