Crocus Technology, a leading developer of magnetic semiconductors, today announced its Magnetic-Logic-Unit (MLU) architecture, a scalable evolution of Crocus’ Thermally Assisted Switching™ (TAS) technology, that permits practical implementation of advanced logic and memory capabilities, a first for the industry. This innovation will expand the market for Crocus’ magnetic technology by opening up new applications in high density data storage, secure commerce and communications, high performance network processing and high temperature automotive and industrial uses.
Traditional magnetic memories are based on arrays of memory cells where each cell contains two magnetic layers in a stacked configuration. The first layer, often called the reference layer, is always magnetized in one direction. The second layer, called the storage layer, is either magnetized in the same direction as the reference layer to store a “1”, or the opposite direction to store a “0”. Crocus’ new MLU is based on its proven TAS technology to provide unprecedented stability to the stored data in normal operation. By leveraging this unique stability feature, the reference layer in the MLU architecture can be configured with fixed magnetization to implement a traditional NOR function, with floating magnetization to implement a NAND function, or with driven magnetization to implement an XOR function.
In high density memory applications, MLU opens the way to implementation of NAND configurations in magnetic memory, which was previously possible only in Flash memory technology. MLU NAND memory can be two to four times denser than conventional magnetic memory with the added benefit of full random access. Crocus’ MLU XOR, called Match-In-Place™, implements ultra-secure compare and encryption functions, making smart cards, identity cards, SIM cards, and near-field communications (NFC) devices tamper-proof. Match-In-Place also implements the search and compare functions required in network routing applications and high performance computing and can achieve up to fifty times the density of conventional CMOS hardware search processors. In addition, MLU in all its configurations is capable of normal operation at temperatures up to 200?C, making it ideal for use in automotive and industrial electronics.
“MLU has the potential to replace SRAM, DRAM, NAND, NOR and OTP in many stand alone and embedded memory products,” said Bertrand F. Cambou, executive chairman of Crocus Technology. “Because MLU’s NOR, NAND and XOR capabilities are built on a single wafer manufacturing process with different design architectures, they can be easily integrated into System- on-Chip (SOC) implementations.”
MLU is fully compatible with Crocus’ current wafer manufacturing process. Crocus will establish volume production of MLU based products in 130nm at its foundry partner Tower Jazz Semiconductor, as well as at its new Russian subsidiary Crocus Nano Electronics (CNE) for 90nm, 65nm, 45nm, and smaller lithography. Both will be based on magnetic technology developed in Crocus’ Grenoble facility in cooperation with its clean room partner Minatec.
The TA-MRAM writing was tested and validated in the dynamic regime down to 500ps write pulses.
The holy grail of MRAM research is the ultimate replacement of DRAM. The Spin Torque technologies in the laboratory today provide a path to bit cells in the 10 f2 range. As MRAMs approach this bit cell density, applications that use DRAM will look to MRAM as a higher functionality, cost-effective alternative to conventional DRAM. Helping to spur this possible transition are concerns in the DRAM industry that the storage capacitor technologies used in so many previous generations of DRAM will start running into serious scaling problems below 45nm. These advanced MRAM technologies threaten a serious shift in the roughly $50 billion in yearly DRAM revenue.
In summary, SOC’s may be possible in the near term, with embedded MRAM that enables both non-volatile capability and an SRAM replacement that is three to four times denser than current 6-transistor memory technology, with only modest changes to the underlying CMOS processes. At a reasonable level of maturity, MRAM will become a cost effective alternative to DRAM. It thus has the potential to displace tens of billions of dollars of DRAM business, while at the same time providing system designers exciting new capabilities leveraging their high speed and infinite-endurance non-volatility. The physics and process research that is underway today pushes the MRAM cost roadmap into intersection with the DRAM roadmap. The successful development of these second generation MRAM technologies will touch businesses and consumers everywhere.