Planar transistors are given a new lease on life

Suvolta released its Powershrink CMOS transistor technology that it claims will reduce the power consumption of CMOS circuits. The firm’s Powershrink technology uses Deeply Depleted Channel (DDC) CMOS transistors and DDC-optimised circuits and design techniques.

The use of DDC allows chipmakers to reduce power supply voltages by up to 30 per cent and reduce power leakage by 80 per cent. Most importantly, DDC technology can be used in the fabrication of CPUs and system-on-chip packages built for use in smartphones and tablets.

Suvolta’s DDC technology has been picked up by Fujitsu for its 65nm process node. 65nm is almost prehistoric when you consider that Intel showed off its 22nm Tri-gate transistor technology in May. However Suvolta claims that the leakage on its 65nm process node is less than that of Intel’s 45nm process node. That’s an impressive claim that will no doubt be put to the test as chip firms will want to get away with lower fab costs.

Suvolta was keen to stress the ease with which firms can adopt DDC technology. After all it’s no use if the cost of implementing DDC offsets any yield gains. To that end, Suvolta said that its DDC technology does not require new equipment or materials in fabs and uses standard design tools and flows.

Bruce McWilliams, president and CEO of SuVolta said, “Lowering semiconductor power consumption has far reaching benefits for the range of applications and products that can be developed. Suvolta is very pleased to be providing the industry with a technology platform that is advancing the possibilities from continued scaling of planar, bulk CMOS technology.”

McWilliams’ mention of planar CMOS technology is a reference to Intel’s announcement that it will use ‘3D’ transistors for its 22nm process node. In making that announcement, Intel said that it could not move to 22nm without it, sounding the death knell for traditional ‘2D’ planar transistors.

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