IBM’s paper is set to move that on towards a manufacturable technology based on CMOS-compatible fabrication on 200-mm diameter wafers, according the abstract released by the organizers.
Cross-sectional scanning electron microscope micrograph of the post-CMP wafer showing the inverted-T gate structure described in the paper.
Because all the carbon chemical bonds are used within a perfect graphene sheet it has an inherently inert surface making the fabrication of a dielectric layer above it – to insulate the gate – difficult. IBM’s approach has been to invert the usual manufacturing process and define gate structures first on silicon wafers and then transfer graphene layers fabricated using chemical vapor deposition to the silicon. After defining the areas of graphene IBM was able to attach source and drain contacts to the graphene to complete FET structures.
The frequency doubler integrates multiple field effect transistors and radio frequency passives and demonstrated a conversion gain of approximately -25db at an output frequency of 2-GHz, according to data released by the IEDM organizers.
The four images show: (a) an 8-inch graphene FET wafer; (b) single die; (c) SEM image of a typical fully processed device and (d) an enlarged view of the device showing the embedded gate structure with two-finger design. Except for the CVD graphene transfer, all processing was done in a conventional 200-mm wafer fab
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