IBM Makes Revolutionary Racetrack Memory Using Existing Tools and develop graphene and carbon nanotube devices

Technology Reveiw – IBM has shown that a revolutionary new type of computer memory—one that combines the large capacity of traditional hard disks with the speed and robustness of flash memory—can be made with standard chip-making tools.

IBM press release – Researchers Demonstrate Future of Computing with Graphene, Racetrack and Carbon Nanotube Breakthroughs

Prototypes developed for first time in real-world manufacturing environments are critical step towards transferring research into commercial devices.

IBM researchers are detailing the first Racetrack memory device integrated with CMOS technology on 200mm wafers, culminating seven years of physics research.

The researchers demonstrated both read and write functionality on an array of 256 in-plane, magnetized horizontal racetracks. This development lays the foundation for further improving Racetrack memory’s density and reliability using perpendicular magnetized racetracks and three-dimensional architectures.

This breakthrough could lead to a new type of data-centric computing that allows massive amounts of stored information to be accessed in less than a billionth of a second.

The work is important because the cost and complexity of manufacturing fundamentally new computer components can often derail their development. Racetrack memory could someday supersede flash in terms of density and cost.

Racetrack memory could end up competing with memristors for future computer memory technology dominance.

Memory milestone: These nanowires are part of a prototype chip for a novel form of data storage that could fit more information into a smaller space than today’s technology.


This first-ever CMOS-compatible graphene device can advance wireless communications, and enable new, high frequency devices, which can operate under adverse temperature and radiation conditions in areas such as security and medical applications.
The graphene integrated circuit, a frequency multiplier, is operational up to 5 GHz and stable up to 200 degrees Celcius. While detailed thermal stability still needs to be evaluated, these results are promising for graphene circuits to be used in high temperature environments.
New architecture flips the current graphene transistor structure on its head. Instead of trying to deposit gate dielectric on an inert graphene surface, the researchers developed a novel embedded gate structure that enables high device yield on a 200mm wafer.

Carbon Nanotubes

IBM researchers today demonstrated the first transistor with sub-10 nm channel lengths, outperforming the best competing silicon-based devices at these length scales.

While already being considered in varied applications ranging from solar cells to displays, it is expected that computers with in the next decade will use transistors with a channel length below 10 nm, a length scale at which conventional silicon technology will have extreme difficulty performing even with new advanced device architectures. The scaled carbon nanotube devices below 10nm gate length are a significant breakthrough for future applications in computing technology.

While often associated with improving switching speed (on-state), this breakthrough demonstrates for the first time that carbon nanotubes can provide excellent off-state behavior in extremely scaled devices– better than what some theoretical estimates of tunneling current suggested.

The new racetrack prototype was made at IBM’s labs in Yorktown, New York, using a manufacturing technique known as CMOS, which is widely used to make processors and various semiconductor components. This proves that it should be feasible to make racetrack memory commercially, says Parkin, although much refinement is still needed.

The nickel-iron nanowires at the heart of the prototype were made by depositing a complete layer of metal onto an area of the wafer, and then etching away material to leave the nanowires behind.

The wires are approximately 10 micrometers long, 150 nanometers wide, and 20 nanometers thick. One end of each nanowire is connected to circuits that deliver pulses of electrons with carefully controlled quantum-mechanica­l “spin” to write data into the nanowire as magnetic stripes. The other end of each nanowire has additional layers patterned on top that can read out data by detecting the boundaries between stripes when they move past.

The IBM work doesn’t yet demonstrate all of the key components that make racetrack memory desirable. “They have only demonstrated that it is possible to move a single bit in each nanowire,” he explains.

Much of the promise of the technology lies in the potential to store many bits—using many magnetic stripes—in a single tiny nanowire, to achieve very dense data storage. Ravelosona suggests that the material used to make the nanowires in the new IBM device lacks the right magnetic properties to allow that.

Background on the potential of Racetrack memory

Racetrack memory at wikipedia – Current projections suggest that racetrack memory will offer performance on the order of 20-32 ns to read or write a random bit. This compares to about 3,000,000 ns for a hard drive, or 6-40 ns for conventional DRAM. The authors of the primary work also discuss ways to improve the access times with the use of a “reservoir,” improving to about 9.5 ns. Aggregate throughput, with or without the reservoir, is on the order of 250-670 Mbit/s for racetrack memory, compared to 102400 Mbit/s for dual channel DDR2 DRAM, 1000 Mbit/s for high-performance hard drives, and much slower performance on the order of 30 to 100 Mbit/s for flash memory devices. The only current technology that offers a clear performance benefit over racetrack memory is SRAM, on the order of 2 ns, but is much more expensive and far lower density

There are two ways to arrange racetrack memory. The simplest is a series of flat wires arranged in a grid with read and write heads arranged nearby. A more widely studied arrangement uses U-shaped wires arranged vertically over a grid of read/write heads on an underlying substrate. This allows the wires to be much longer without increasing its 2D area, although the need to move individual domains further along the wires before they reach the read/write heads results in slower random access times. This does not present a real performance bottleneck; both arrangements offer about the same throughput. Thus the primary concern in terms of construction is practical; whether or not the 3D vertical arrangement is feasible to mass produce.

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