IEDM ponders radically different computers

The International Electron Devices Meeting is an annual conference in which the world’s foremost device researchers describe a variety of conventional and unconventional transistor paradigms. The semiconductor industry is starting to mass produce 22 nanometer transistors, and should begin volume production of 14 nanometer microchips by 2014. The 2011 IEDM focused both on continuing CMOS scaling down to 5 nm gate lengths as well as a host of potential post-CMOS technologies. Researchers from Purdue, MIT, and Berkeley presented a paper on Ultimate Device Scaling and concluded that:

“Despite Multiple Leakage Paths, non-planar devices with a multi-gate architecture and an extremely narrow cross-section can be expected to still work as good switches, even with a 5 nm gate length, provided that they exhibit a large enough band gap and transport effective mass and that their gate contact can modulate the electrostatic potential of the source and drain extensions to effectively increase the gate length.”

Below 10 nm, however, the viability of CMOS technology is unclear, and a variety of substitutes are being examined. In particular, graphene has emerged as the candidate with the highest likelihood of displacing silicon CMOS. Switching speeds as high as 155 GHz have been reported, and 200 mm wafers have been fabricated. However, the lack of a bandgap for graphene means that graphene is currently unsuitable for digital applications. Researchers are also making progress on using carbon nanotube transistors, and are implanting them on silicon wafers. Stanford researchers reported their progress making digital circuits, claiming that “the building blocks required for an elementary computing system have been demonstrated using CNFETs.” These researchers noted that CNFETs at the 11nm node should outperform their silicon counterparts in speed and power consumption. Papers were also given on high mobility “gate all around” nanowire devices, which have been experimentally demonstrated and which could prove to be the optimal device for ultimately miniaturized logic switches. Researchers have even fabricated Indium gallium arsenide nanowires with wraparound gates. Although the era of planar silicon CMOS devices may soon be ending, a plethora of options exist to continue Moore’s law for at least the next decade.

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