The researchers developed a vertically integrated hybrid electronic circuit by combining the novel memristor developed at the University of Michigan with wafer scale heterogeneous process integration methodology and CMOS read/write circuitry developed at HRL. “This hybrid circuit is a critical advance in developing intelligent machines,” said HRL SyNAPSE program manager and principal investigator Narayan Srinivasa. “We have created a multi-bit fully addressable memory storage capability with a density of up to 30 Gbits/cm2, which is unprecedented in microelectronics.”
Industry is seeking hybrid systems such as this one, the researchers say. Dubbed “R-RAM,” they could shatter the looming limits of Moore’s Law, which predicts a doubling of transistor density and therefore chip speed every two years.
Ultimately the team plans to scale the neuromorphic chip to support millions of neurons and billions of synapses, thereby enabling the development of intelligent machines that can learn from their environments and exhibit complex behaviors. The technology has numerous real-world applications in complex computing including visual perception, planning, decision making and navigation.
Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.
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