HPCWire covers the Corona chip as well. HP has been devising a manycore chipset, which would outrun the average-sized HPC cluster of today. The design represents a radical leap in performance, and if implemented, would fulfill the promise of exascale computing.
The architecture, known as Corona, first conceived back in 2008, consists of a 256-core CPU, an optical memory module, integrated nanophotonics and 3D chip stacking employing through-silicon-vias (TSVs). At peak output, Corona should deliver 10 teraflops of performance. That’s assuming 16 nm CMOS process technology, which is expected to be on tap by 2017.
The Corona design is aimed squarely at data-intensive types of application, whose speed is limited by the widening gap between CPU performance and available bandwidth to DRAM — the so-called memory wall. Basically any workload whose data does not fit into processor cache is a candidate. This includes not just traditional big data applications, but also a whole bunch of interesting HPC simulations and analytics codes that have to manipulate large or irregular data sets, and are thus memory-constrained.
Corona contains 256 cores, each supporting up to four threads simultaneously. The Corona cores themselves are nothing exotic. The HP researchers originally assumed low-power Intel x86 Penryn and Silverthorne CPU core architectures for their design simulations, but presumably ARM or other low-power designs could be substituted.
The processor is divided into 16 quad-core “clusters,” with an integrated memory controller on every cluster. The rationale for the hierarchy is to ensure that memory bandwidth grows in concert with the core count and local memory access maintains low latency.
The processor is stacked with the memory controller/L2 cache, the analog electronics and the optical die (which includes on-chip lasers). Everything is hooked together by a 20 TB/sec dense wavelength division multiplexing (DWDM) crossbar, enabling cache coherency between cores, as well as superfast access to that cache.
Energy efficiency, in particular, is a hallmark of photonic communication. The HP researchers calculate that a memory system using an electrical interconnect to drive 10 GB/sec of data to DRAM would take 80 watts. Using nanophotonics and DRAMs optimized to read or write just a cache line at a time, they think they achieve the same bandwidth with just 8 watts.
Using the SPLASH-2, the second version of the Stanford Parallel Applications for Shared Memory benchmark suite, the HP researchers demonstrated a performance improvement of 2 to 6 times on Corona compared to a similar system outfitted with an electrical interconnect, and those speed increases were achieved using much less power. They also showed significant performance improvements on five of the six HPC Challenge benchmarks: PTRANS (22X), STREAM (19X), GUPS (19X), MPI (19X), FFT (2X). DGEMM, which is not bandwidth limited, showed no improvement.
It’s not all a slam dunk, however. 3D chipmaking and TSV technology is still a work in progress. And integrating photonic hardware using CMOS is in its infancy. But integrated photonics, 3D chip stacking, and the use of low-power cores for computation are all hot technologies now, especially for those in the supercomputing community looking down the road to exascale. The UHPC project (now apparently stuck in Phase 1) that was aimed at developing low-power extreme-scale computing, attracted proposals from Intel, MIT, NVIDIA, and Sandia that incorporated one or more of these technologies.
With Corona though, you get the whole package, so to speak. But all of the work to date appears to be with simulated hardware, and there was no mention in any of the research work of plans to create a working prototype. So whether this is destined to remain a research project at HP or something that gets transformed into a commercial offering remains to be seen.