Three competing semiconductors at the 8 nanometer node

EETimes – The possible pathways down to the 8-nanometer semiconductor fabrication node were detailed last week at the IEEE International Symposium on Physical Design (ISPD).

The conference program and links to slides are here

The pathway is fraught with engineering peril as three competing technologies tool up for mass production capabilities. However, keynote speaker Burn Lin, a TSMC distinguished Fellow, claimed that one of three alternatives was sure to surmount the downward scaling hurdles to 8-nm design rules.

The three alternative pathways were
1) 193-nanometer immersion lithography supplemented with multi-patterning
2) extreme ultraviolet (EUV) lithography
3) e-beam lithography.

Immersion is closest to realization, according to Lin, but only if it can surmount spiraling cost barriers. EUV at the 13.5-nanometer wavelength has already been demonstrated capable of sub-20-nanometer design rules, but needs better focusing mechanisms and higher output light sources to overcome reflectivity of optics as low as 65 percent. E-beam is known to be able to achieve the 8-nanometer node today, but is a last-resort technology due to its slow speed and low throughput.

Mapper Lithography (Delft, the Netherlands) uses more than 10 thousand beamlets operating simultaneously as it aims for migration down to the 8-nanometer node. Source: Mapper Lithography

To solve e-beam’s throughput problems, Lin described efforts to use massively parallel e-beams at KLA-Tencor Corp. (Milpitas, Calif.) and Mapper Lithography BV (Delft, the Netherlands), allowing thousands of simultaneous beams to speed throughput, albeit only if reliability, uniformity and accuracy can be improved.

One of the best paper nominees at this year’s ISPD was from professor Yao-Wen Chang’s group at National Taiwan University, which addressed the overheating problems of massive e-beam writing processes, achieved by reordering the writing sequence to better control dimensional distortions.

One of the invited talks at ISPD was given by research scientist Shayak Banerjee at IBM Research (Austin, Texas) who described how shape tolerance on layout polygons could help advanced node lithography. He also described two manufacturing methods for harnessing these polygons using mask- and layout-optimization.

Memristors in 3-D

A second invited paper by professor Tim Cheng at the University of California at Santa Barbara described how 3-D techniques could realize the dream of semiconductor memristors.

Using a hybrid 3-D integration technique, Cheng’s memory structure sandwiched the memristive material between the perpendicular lines of a crossbar at the astronomical density of 100,000 gigabits-per-square-centimeter with 1 billion gigabits-per-second bandwidth.

The biggest challenge of the design was to overcome the mismatch between the fine-grain dimension of the crossbar-based devices and the interface pins of the chip, which Cheng overcame with novel 3-D vias that were tilted with respect to the interface pins.

The best paper award was given to Professor Chirs Chu at Iowa State University, who proposed an algorithm for determining the optimal circuit block shape in VLSI fixed-outline floor-planning, achieving a 10-to-100 increase over previous state-of-the-art techniques.

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