DARPA Synapse Project Status

SyNAPSE is a DARPA-funded program to develop electronic neuromorphic machine technology that scales to biological levels. More simply stated, it is an attempt to build a new kind of computer with similar form and function to the mammalian brain. Such artificial brains would be used to build robots whose intelligence matches that of mice and cats.

SyNAPSE is a backronym standing for Systems of Neuromorphic Adaptive Plastic Scalable Electronics. It started in 2008 and as of June 2012 has received $102.6 million in funding. It is scheduled to run until around 2016. The project is contracted to IBM, HRL Laboratories, and four US universities: California Merced, Columbia University Medical Center, Cornell, and Wisconsin-Madison. he program is currently progressing through phase 2 – as of June 2012.

This involves, among other things, designing a multi-chip system capable of emulating 1 million neurons and 1 billion synapses. The program requirements are that no phase last longer than 18 months. This means the million-neuron design should be completed by February 2013. Construction of the system will come in phase 3, to be completed around August 2014.

The ultimate aim is to build an electronic microprocessor system that matches a mammalian brain in function, size, and power consumption. It should recreate 10 billion neurons, 100 trillion synapses, consume one kilowatt (same as a small electric heater), and occupy less than two liters of space.


Aug 18, 2011 – A neuromorphic chip was unveiled containing 256 neurons and ~250,000 synapses. It could learn to recognise handwritten digits and play a game of pong.

June 6, 2012 – Paper published describing how the SyNAPSE project’s 256-neuron neuromorphic chip was used to capture essential functional properties of olfactory bulb glomerular-layer computations.

HRL Labs announced in December 2011 that they have built a memristor array integrated on top of a CMOS chip. This was the first ever functioning demonstration of such a memristor array.

Due to the high circuit density and low power requirements, memristor technology is considered important for the continuation of Moore’s Law. The HRL chip has a multi-bit fully-addressable memory storage capability with a density of up to 30 Gbits/cm2. Such density is unprecedented in microelectronics.

The simultaneous memory storage and logic processing capability of memristors makes them very suitable for neuromorphic computing. The memory and logic units are one and the same, much like the neural circuits of the brain.

HRL’s hybrid crossbar/CMOS system can reliably store 1,600 pixel images using a new programming scheme. Ultimately the team plans to scale the chip to support emulation of millions of neurons and billions of synapses.

Nanoletters – A Functional Hybrid Memristor Crossbar-Array/CMOS System for Data Storage and Neuromorphic Applications

Phase 2
* Chip fabrication of over 10^10 synapse/cm2, over 10^6 neurons/cm2
* Design a complete neural system of ~10^10 synapses and ~10^6 neurons for simulation testing
* Design a corresponding single chip neural system of ~10^10 synapses and ~10^6 neurons
* Demonstrate a simulated neural system of ~10^6 neurons performing at mouse level in the virtual environment
* Expand the Sensory Environment to include training and evaluation of Auditory Perception and Proprioception
* Expand the Navigation Environment to include features stressing Competition for Resources and Survival
* Demonstrate a selectable range of complexity corresponding roughly to the capabilities demonstrated across a ~10^6 range in brain size mammalian species

Phase 3

March 2013 – Phase 3 to begin (estimated date)

* Fabricate a single-chip neural system of ~10^6 neurons (1 million) into a fully functioning assembly.
Show mouse-level performance in a virtual environment.
* Design neural system of ~10^12 synapses (1 trillion) and ~10^8 neurons (100 million) for simulation testing
* Design a corresponding single-chip neural system of ~10^12 synapses (1 trillion) and ~10^8 neurons (100 million)
* Demonstrate a simulated neural system of ~10^8 neurons performing at cat level
* Add touch to the sensory environment.
* Add a symbolic environment.

Phase 4

October 2014 – Phase 4 to begin (estimated date)

The final deliverable metric is the fabrication of a multi-chip neural system of 10^8 neurons (100 million) and install this in a robot that performs at cat level. Estimated to begin between late 2013 and late 2015. Estimated completion date, late 2014 to late 2017.

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