We present a design-scheme for ultra-low power neuromorphic hardware using emerging spin-devices. We propose device models for ‘neuron’, based on lateral spin valves that constitute of nano-magnets connected through metal-channels. Such magneto-metallic neurons can operate at ultra-low terminal voltage of ~20 mV, resulting in small computation energy. Use of domain wall magnets as programmable ‘synapse’ and as ‘integrating-neurons’ is proposed. Magnetic tunnel junctions are employed for interfacing the spin-neurons with charge-based devices like CMOS, for large-scale networks. Device-circuit co-simulation-framework is used for simulating such hybrid designs, in order to evaluate system-level performance. We present the design of different classes of neuromorphic architectures using the proposed scheme that can be suitable for different applications like, analog-data-sensing, data-conversion, cognitive-computing, associative memory, programmable-logic and analog and digital signal processing. We show that the spin-based neuromorphic designs can achieve 15X-300X lower computation energy for these applications, as compared to state of art CMOS designs.
(a) On sensor image processing architecture (b) SAR-ADC using spintronic neuron, and simulation results for (c) edge-detection, (d) half-toning, and (e) digitization (using spin-CMOS hybrid SAR-ADC : lowering ΔV increases % noise and hence degrades accuracy)
By the end of 2012, there will likely be integrated one square neuromorphic chips with about ~10 billion synapses and ~1 million neurons. This work is in the DARPA Synapse project. In 2015, the neuromorphic chips are targeted to have 100 times more capability. The military is developing neuromorphic chips for autonomous, unmanned, robotic systems and natural human-machine interfaces and diverse sensory and information integration applications in the defense and civilian sector.
We proposed spin-based device models for neuron that can facilitate the deign of ultra-low power neuromorphic-computation hardware. We developed device-circuit co-simulation framework to assess the performance of heterogeneous neuromorphic designs that employ the proposed neurons. We obtained highly promising estimates for common data processing applications that show 20X- 300X improvement in computation energy as compared to state of art CMOS design. The research presented in this work involves device circuit-architecture co-design and can lead to a comprehensive design solution for neuromorphic hardware.
They base their design on two technologies: lateral spin valves and memristors. Lateral spin valves are tiny magnets connected via metal wires that can switch orientation depending on the spin of the electrons passing through them. We’ve looked at memristors many times on this blog. These are fundamental electronic devices that act like resistors with memory.
Augustine and co argue that that the architecture they’ve designed works in a similar way to neurons and can therefore be used to test various ways of reproducing the brain’s processing ability.
The icing on the cake, they say, is that spin valves operate at terminal voltages measured in milliVolts, that’s significantly less than conventional chips.