Progress to Wafer scale graphene transistors and electronics

Physicists from Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) have developed a procedure for manufacturing integrated high-performance circuits from graphene and silicon carbide.

Graphene is a one-atom-thick layer of graphite. The material has a several unique properties and researchers around the world believe it has great potential in electronics. As early as 2009, FAU researchers devised a method for large-area production of graphene on a silicon carbide layer – however they have not yet been able to use graphene for producing high-performance transistors with excellent characteristics.

In their latest study, Professor Heiko Weber from the Department of Applied Physics at FAU and his team have made a breakthrough to solve this limitation. Professor Weber and his research team adopted a different approach than most of their international colleagues: “We are still using a silicon carbide surface to form the graphene but our technique uses the surface as a conductive rather than insulating layer,” explains Professor Weber. “This allows us to use the properties of both materials for electronic processes.”

The graphene, a two-dimensional honeycomb structure consisting of carbon atoms, is formed from a silicon carbide crystal. It is then shaped into conductor paths and partly treated with hydrogen. This causes the electrical energy (image: blue electrons) to flow over the graphene contacts (black) into the silicon carbide crystal where it is regulated by the hyrdrogen-treated graphene contacts (red/yellow). Image: J. Jobst, S. Hertel

Nature Communications – Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics

Thanks to intricate structures and treatment with hydrogen, the FAU physicists are able to manipulate the surface between graphene and silicon carbide to form a transistor which has excellent characteristics and is fast. “The most important innovation, however, is that the transistor consists of only two materials, which are extremely robust,” says Heiko Weber. “This technique is excellent for designing individual transistors and developing complex circuits.”

ABSTRACT – Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10,000 and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

Two different epitaxial graphene materials combined to a monolithic transistor.

In summary, we present an integrated scheme for a transistor with high on/off ratios using epitaxial graphene on 6H-SiC (0001). It is monolithic in the sense that it includes and relies on the entire system graphene, SiC and its interfaces, and furthermore, that devices can be carved out of a single epitaxial graphene/SiC chip. With appropriate adaptations, they can be fabricated side-by-side with present epitaxial graphene high-frequency architectures8 (for which it provides the missing switch), and also with existing SiC high-power devices, with low fabrication effort. We have reached on/off ratios up to 74,000 (or even more than 600,000 when comparing minimum and maximum current ID at UTG=−0.2 V and 0.6 V, respectively, for UBG=−3.5 V, USD=1 V and T=220 K). We consider this device as a proof of concept. The presented device performance is not fundamentally limited and may be tailored according to specific requirements. In particular, the contact resistances can be improved by four orders of magnitude by contact implantation. Different intercalation conditions, variation of off-angle of the substrate, design optimisation, and so on, are expected to lead to uniform and therefore higher effective Schottky barriers. This will allow for higher currents, higher operation speed and higher operation temperatures.

The concept’s particular strength, however, lies in the following property: within the same processing steps, many epitaxial graphene transistors can be connected by graphene strip lines (the interface from contact graphene to gate graphene is electrically transparent) along with graphene resistors and graphene/SiC Schottky diodes, and therefore complex circuits can be built up. As a special feature of graphene in contrast to semiconductors, we anticipate that even a complete logic is feasible.

(a) We have characterized the ohmic contacts of MLG on SiC. The left inset shows the geometry of the CTLM pattern. The grey ring corresponds to the SiC channel with parametrically varied length d. The inner and outer parts are used as contacts. The right inset corroborates the linearity of the I–V characteristics (ohmic contacts), despite a very low doping of the semiconductor. The slope Rcorr (corrected for cylindric geometry) of the corresponding I–V curves is plotted against d in the main figure. From the linear Rcorr(d) dependence contact and sheet resistance, ρC and RS, respectively, are derived. (b) I–V characteristics of a QFBLG/SiC junction with ohmic counter electrode. The rectifying Schottky behaviour justifies the use as gate graphene. A Schottky barrier height B,IV=0.9 eV is extracted from the forward characteristics (shaded area, same data shown in upper inset). B,CV=1.57 eV is extracted from C–V data (lower inset) on the same device.

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