3D CMOS Memristor Circuits

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There is work towards creating 3D CMOs memristor circuits

Maximum Number of Layers
• Each layer has N^2 cells.
• There are r^2– 1 cross points per cell.
• That gives us a total of N^2 * (r^2 – 1) cross points per layer.
• The double decoding scheme allows us to address up to N^4 locations
• Which means that we can (potentially) have up to N^2 /(r^2 – 1) crossbar layers.

If Successful, 3D Hybrids Can Achieve…..
• Unprecedente dmemory density
– Footprint of a nano‐device is 4F nano 2/K, for K vertically integrated crossbar layers
– Potentially up to 10^14 bits on a single 1‐cm^2 chip
• Enormous memory bandwidth
– Potentially up to 10^18 bits/second/cm2
• At manageable power dissipation
• With abundant redundancy for yield/reliability

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