Technical publications related to the Janusz Bryzek of Fairchild Semiconductor Keynote that talked about 180 nm transistors printed for $25 per square meter

So the EETimes reported on the keynote address of Janusz Bryzek of Fairchild Semiconductor at Semicon West where Janusz mentioned –

UC Berkeley is now developing printed transistors at 180nm. The technology could deliver chips costing $25 a square meter, not the $25,000 per square meter of current processes, again a huge cost reduction that is mind boggling.

There is a 121 page PHd dissertation by Huai-Yuan Tseng (UC Berkeley) who is in Vivek Subramanian group where he talks about scaling of inkjet printing of transistor technologies. The Dec 2011 paper talks about 200 nanometer features. Presumably they have improved it to 180 nm in the last 19 months. Plus there is a lag in the production of a dissertation paper.

Roll to Roll Printing of transistors

Advanced Materials – High-Performance Printed Transistors Realized Using Femtoliter Gravure-Printed Sub-10 μm Metallic Nanoparticle Patterns and Highly Uniform Polymer Dielectric and Semiconductor Layers

Using a novel high-speed, femtoliter-scale, micro-gravure printing with unprecedented scaling to the sub-10 μm regime and appropriately formulated, characterized, and optimized nanoparticle and polymer ink materials, highly scaled organic thin-film-transistors (OTFTs) are realized. They have excellent DC and AC characteristics and achieve record transition frequencies of 300 kHz, which opens up new classes of applications.

The thesis talks about 200 nm features, the roll to roll work would suggest large volume and cheap transistors. Presumably Janusz Bryzek of Fairchild Semiconductor is in closer contact with Vivek as to how this can all fit together for 180 nm transistors at $25 per square meter.

Vivek Subramanian group publications.

Advanced Materials – Transparent High-Performance Thin Film Transistors from Solution-Processed SnO2/ZrO2 Gel-like Precursors (Nov 2012)

This work employs novel SnO2 gel-like precursors in conjunction with sol–gel deposited ZrO2 gate dielectrics to realize high-performance transparent transistors. Representative devices show excellent performance and transparency, and deliver mobility of 103 cm2 V−1 s−1 in saturation at operation voltages as low as 2 V, a sub-threshold swing of only 0.3 V/decade, and Ion/Ioff of 10^4∼10^5.

Dissertation Summary

There has been a great interest in the realization of low-cost electronic applications such as item-level RFID tags and smart labels. Printed electronics has become the most promising technology due to its lithography- and vacuum-free processing. In this regard, solution-processed materials have been advanced rapidly to enhance the performance of printed devices. However, the poor resolution of state-of-the-art printing techniques such as inkjet and gravure printing has necessitated the use of large channel lengths in transistors and large gate to source/drain overlap to compensate for the poor layer-to-layer registration capability. These large dimensions have limited the speed improvement in printed transistors, despite the improvements in materials. Therefore, this thesis focuses on circumventing the printing resolution challenges using novel printing techniques. Scaling of the critical dimensions as well as improvement of the switching speed was achieved with a purely printing process.

To reduce the parasitic capacitance of printed transistors, a wetting-based roll-off technique has been applied to achieve self-alignment of transistor source/drain electrodes to the gate, resulting in a minimum overlap. Minimum overlap of 0.47 μm was achieved, contrasted to the over 10 μm typically required in conventional printed transistors. The technique has also been applied to realize a fully printed inverter circuit. For further scaling of the transistor dimension, shrinking of the printed gate electrodes is required. Therefore a novel printing technique combining inkjet printing and mechanical pen dragging was proposed. Printed gate lines as narrow as 2.75 μm were demonstrated. Printed transistors combining the highly-scaled gate lines and self-alignment were demonstrated. Transistors with channel lengths as small as 200 nm to 2.75 μm showed the highest cut-off frequency reported to date of 1.6 MHz. The performance is expected to be improved further by using the most advanced materials. This high speed operation will enable the realization of fully printed RFID and other printed applications in the foreseeable future.

In 2011, an interview wit Vivek indicates that there was still work needed to perfect the materials

The materials sets are not complete yet. We need to better integrate semiconductors, dielectrics and conductors. The printed transistors made in my lab are among the fastest anyone makes today, but the way we get there is through a combination of commercially available and homemade processes.

Janusz Bryzek of Fairchild Semiconductor seems to suggest that those materials and scaling issues are conceptually resolved and there is now work to integrate the processes towards high volume printed 180nm transistors.

The second hurdle is the necessity of improving our tools and process technologies and the third if for applications.
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