IBM Chip will help enable Internet speeds at 200 – 400 Gigabits per second (Gb/s) with extremely low power

IBM announced that it has achieved a new technological advancement that will help improve Internet speeds to 200 – 400 Gigabits per second (Gb/s) at extremely low power.

The speed boost is based on a device that can be used to improve transferring Big Data between clouds and data centers four times faster than current technology. At this speed 160 Gigabytes, the equivalent of a two-hour, 4K ultra-high definition movie or 40,000 songs, could be downloaded in only a few seconds.

Scientists at IBM Research and Ecole Polytechnique Fédérale de Lausanne (EPFL) have been developing ultra-fast and energy efficient analog-to-digital converter (ADC) technology to enable complex digital equalization across long-distance fiber channels.

An ADC converts analog signals to digital, approximating the right combination of zeros and ones to digitally represent the data so it can be stored on computers and analyzed for patterns and predictive outcomes.

For example, scientists will use hundreds of thousands of ADCs to convert the analog radio signals that originate from the Big Bang 13 billion years ago to digital. It’s part of a collaboration called Dome between ASTRON, the Netherlands Institute for Radio Astronomy, DOME-South Africa and IBM to develop a fundamental IT roadmap for the Square Kilometer Array (SKA), an international project to build the world’s largest and most sensitive radio telescope.

The 64 GS/s (giga-samples per second) chips for Semtech will be manufactured at IBM’s 300mm fab in East Fishkill, New York in a 32 nanometer silicon-on-insulator CMOS process and has an area of 5 mm2. This core includes a wide tuning millimeter wave synthesizer enabling the core to tune from 42 to 68 GS/s per channel with a nominal jitter value of 45 femtoseconds root mean square. The full dual-channel 2×64 GS/s ADC core generates 128 billion analog-to-digital conversions per second, with a total power consumption of 2.1 Watts.

The scientific paper is entitled, “A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm Digital SOI CMOS” by Lukas Kull, Thomas Toifl, Martin Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici.

If you liked this article, please give it a quick review on ycombinator or StumbleUpon. Thanks

Subscribe on Google News