Designs for 10 nanometer FinFETs will be presented in June and discussions and research for the 7 nanometer node will also be shown

The newly released program of the VLSI Technology and Circuits conference shows both historic advances and struggles ahead in silicon. The June event will include an early look at a 10 nm FinFET process as well as a discussion of a pile of new technologies all potentially arriving at the 7 nm node.

One paper will demonstrate a way to build silicon photonics in bulk CMOS. A Sony paper will describe a novel curved imager. Neither Intel nor TSMC plan to deliver major papers on their next-generation process technologies at the Honolulu event.

IBM, GlobalFoundries, and Samsung along, with STMicroelectronics and UMC, will describe a 10 nm logic process with the tightest contacted poly pitch (64 nm) and metallization pitch (48 nm) ever reported in FinFETs on both bulk and silicon-on-insulator substrates, according to the program. It uses “intensive” multi-patterning and various self-alignment processes in 193i lithography.

The 10 nm disclosure will come weeks after Samsung announced it licensed a 14 nm FinFET process to GlobalFoundries, which both will use in their merchant foundries.

In a sign of just how hard it is becoming to achieve such advances, a panel will debate whether logic or memory will be first to halt CMOS scaling.

“There is now no question that the nature of scaling today has shifted dramatically. In particular, energy, performance, and perhaps even cost no longer clearly/directly benefit from simple dimensional scaling,” organizers said.

A second panel will provide specifics of the challenges ahead. It notes that 450 mm wafers, extreme ultraviolet lithography III/V channels, and 3D stacks are all expected to arrive at the 7 nm node. Panelists from a wide range of equipment companies and research institutes will debate the impact of facing multiple shifts at the same time.

A paper from Micron, MIT, and the University of Colorado at Boulder will describe what’s billed as the “first functional monolithic integration of a silicon photonic link on bulk CMOS,” geared for a memory chip. They claim the interconnect could be an alternative to 3D chip stacks.

SOURCE – EEtimes

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