Today’s sub-22-nanometer chips are placing a strain on the ability to connect their billions of transistors with traditional copper interconnects. As the number of metallization layers escalates from nine to fifteen or more, the fineness of the copper lines is causing open circuits from voids during manufacturing and electromigration after the chips are deployed. New barrier materials have been proposed to solve the problem, but Applied Materials Inc. of Santa Clara, Calif., claims what is needed is a new technique that encapsulates copper interconnect lines in cobalt, thereby nixing electromigration and extending copper interconnects to the 10-nanometer node.
Through years of research Applied Materials has come up with a solution that it believes can extend copper interconnects to the 10-nanometer node — namely, encapsulating the copper lines in cobalt. Today Applied Materials Endura platform is used to manufacture copper interconnects on chips by first performing a cleaning step to remove particles left over after etching, then using physical vapor deposition (PVD) to add a tantalum nitride/tantalum (TaN/T) barrier layer to prevent copper diffusion into the dielectric. Then it uses PVD to deposit a copper seed — a thin continuous layer of copper alloy — onto the TaN/T barrier. Finally the wafer goes to electroplating and polishing.
Cobalt encapsulation adds two new steps to the copper interconnection process and requires an Endura Volta CVD Cobalt tool.
(Source: Applied Materials)
“Cobalt adheres well to both the TaN barrier and to the copper and works to confine it and prevent electromigration,” Shah tells EE Times. “And it should work all the way to the 10-nanometer node. We have measured a 10-fold improvement in electromigration, and some of our customers have reported 100-fold improvement.”
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