Poet Technologies (market value $220 million) is claiming that gallium arsenide computer chips will finally be ready to drive computer performance as silicon is hitting the wall.
The gallium arsenide integrated circuit market is forecasted to grow to $8 billion in 2017, according to a new report ‘The GaAs IC Market’ by The Information Network. The biggest enabler of the mobile data increase and the most important driver of the GaAs RF IC market is the handset segment. Much of the content of a handset is silicon-based, but power amplifiers (PAs) and switches in the front-end of the phone use GaAs device. The global IC market had sales of $271 billion in 2013.
POET Technologies is a developer of the planar opto-electronic technology (POET) platform for monolithic fabrication of integrated circuit devices containing both electronic and optical elements on a single semiconductor wafer – announced an agreement with a “3rd party foundry” to reproduce and enhance repeatability of the 100-nm scale results obtained at the Company’s labs (the “POET labs”) located at the University of Connecticut (UCONN). The “3rd party foundry” will also assist the POET team in shrinking the 100-nm PET devices and process to a 40-nm feature size.
40 nanometer GaAs compares to 14 nanometer in speed and 10 nanometer in power.
Key benefits of the POET platform include:
* Up to 100x speed improvement over CMOS silicon (silicon hits a “power wall” at about 4 GHz that has limited circuit speeds to about 3.2 GHz over the last 10 years). They can produce small gallium arsenide [GaAs] analog circuits switching at 100 GHz today and 400 GHz in the not too distant future
* 10-100x power efficiency improvement over CMOS silicon (depending on application)
* Flexible application that can be applied to virtually any technical application, including memory, digital/mobile, sensor/laser and electro-optical, among many others
* No retrofit or other modifications to existing silicon fabs required – Since POET/PET are CMOS technologies fabricated using standard lithography techniques; they are easily integrated into current semiconductor production facilities extending the profitable utilization of fabrication equipment and production lines that would otherwise be considered at the end of life.
EETimes has an article on Poet Technologies. Combining standard logic with optical components on the same chip also changes the design methodology, prompting a collaboration with Synopsys, Inc., of Hillsboro, Ore., to help design hybrid electro-optical devices. For instance, an optical loop achieves an ultra-low jitter oscillator with higher bandwidth than silicon, according to POET. By going to multi-wave lengths, POET also aims to build ultra-precise analog-to-digital converters by encoding voltages as wavelengths, resulting in higher resolution and bit rates with reduced power and fewer components.
Other advantages of III-V over silicon is its lower operating voltage — as low as 0.3 volts with electron mobilities as high as 12,000 cm2/ (V·s) achieved by strained quantum wells — lowering the power required to operate III-V chips by 10 times or more, according to POET.
Of course, GaAs wafers are more expensive than Si, but the next generation of Si is already using silicon-on-insulator with fully depleted (SOI-FD) transistors, a technology that costs almost as much as GaAs.
POET has found a way to grow successive layers of InGaAs on GaAs wafers, each with a little more indium, until they achieve a substrate on which both n-type and p-type transistors can be fabricated.
The p-types could ultimately achieve about a 1900 cm2/(V·s) hole mobility in the strained InGaAs quantum well, which is not as high a figure as the n-types, which achieve 8500 cm2/ (V·s). Both are higher than silicon, at 1200 cm2/ (V·s). POET has high hopes that it can eventually boost the n-types to greater than 12,000 in order to realize extremely high digital logic rates with complementary HFETs.
The channels of POET’s transistors are InGaAs, which theoretically could reach 40,000 cm2/ (V·s) if the gallium was reduced to zero (pure bulk InAs). That however is not achievable, according to POET, although it is getting as close as it can. Thus far channels of 53% indium have been achieved and the company believes that 80% indium is ultimately possible.
Poet Technology white paper on Optical Interconnection of high speed circuits.
POET Near Term
POET will implement an optical interface as a single chip to connect existing CMOS processors. The optical interface chip integrates the laser, modulator, modulator driver, detector, receiver amplifiers, SER/DES, CDR and PLL circuits monolithically. Both the DSP and the POET chip are mounted face do close proximity on a Si carrier which forms a single common plane. The carrier has a standard MT connector for a 12 channel fiber ribbon cable for optical I/O. The POET chip connects to the fibers through a proprietary, (patented) mating technique. POET also connects to transmission lines (T/L’s) on the Si carrier through standard solder bumps. The CMOS processor connects to the same T/L’s with solder bumps. The assembly cost is reduced substantially along with the power dissipation. The sizeable speed advantage of strained InGaAs quantum wells increases the bandwidth. Assigning one optical interface to each processor, processors on multiple carriers are connected optically by fiber. The initial OE solution will address requirements for both military and commercial markets.
POET Longer Term
POET implements the processor by replacing all the CMOS gates with CHFET gates. The POET processor will provide its own optical output and also performs the optical receive function so the need for a separate interface chip is no longer required. In addition, the Si carrier is no longer needed as the PCB is constructed with polymer waveguides which then are coupled to the POET output waveguides using same proprietary, (patented) interface technique as above. The polymer guides also connect to optical fiber I/O at a MT fiber ribbon cable connect conjunction with pre-installed Si connectboard are connected by waveguide to transport all high speed signals while standard PCB metal lines handle all lower speed signals. Not only will the cost of packaging this device be substantially reduced but also will its size, weight and power consumption while the data rate continues to expand to the limits of the device performance. These metrics continue to improve with scaling of feature size from the near term values stated above towards the 20nm node since the transmitter and receiver are directly linked to a device size rather than a circuit. Upon completion of a fully functioning optical VLSI circuit, POET will successfully address multiple high speed markets most notably the high processor with embedded memory, the high end optoelectronic switch and the single chip smart
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